LEADER 01780nam  2200361   450 
001 9910687994503321
005 20230627110400.0
024 7 $a10.5772/intechopen.91110
035   $a(CKB)5850000000050239
035   $a(NjHacI)995850000000050239
035   $a(EXLCZ)995850000000050239
100   $a20230627d2022      uy             0
101 0 $aeng
135   $aur|||||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aNetwork-on-Chip $eArchitecture, Optimization, and Design Explorations /$fIsiaka A. Alimi [and three others]
210  1$aLondon :$cIntechOpen,$d2022.
215   $a1 online resource (110 pages) $cillustrations
311   $a1-83968-159-4 
330   $aLimitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems.
517   $aNetwork-on-Chip 
606   $aNetworks on a chip
615  0$aNetworks on a chip.
676   $a621.381531
700   $aAlimi$b Isiaka A.$01367700
801  0$bNjHacI
801  1$bNjHacl
906   $aBOOK
912   $a9910687994503321
996   $aNetwork-on-Chip$93391387
997   $aUNINA