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100   $a20230702d2023      uy             0
101 0 $aeng
135   $aur|||||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 00$aAdvanced Interconnect and Packaging /$fWensheng Zhao, editor
210  1$aBasel :$cMDPI - Multidisciplinary Digital Publishing Institute,$d2023.
215   $a1 online resource (266 pages)
311   $a3-0365-6733-X 
320   $aIncludes bibliographical references.
330   $aUnlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation. At nanoscale technology nodes, interconnect delay and reliability become the major bottlenecks faced by modern integrated circuits. To resolve these interconnect problems, various emerging technologies, including airgap, nanocarbon, optical, and through-silicon via (TSV), have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to increase the integration density. More importantly, 3D integration and packaging also offer the most promising platform to implement "More-than-Moore" technologies, providing heterogeneous materials and technologies on a single chip. The "Advanced Interconnect and Packaging" Special Issue seeks to showcase research papers on new developments in advanced interconnect and packaging, i.e., on the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies. Additionally, there are two interesting papers on carbon nanotube interconnects and interconnect reliability issues.
606   $aPhysics
615  0$aPhysics.
676   $a530
702   $aZhao$b Wensheng
801  0$bNjHacI
801  1$bNjHacl
906   $aBOOK
912   $a9910683386403321
996   $aAdvanced Interconnect and Packaging$93086682
997   $aUNINA