LEADER 03814nam 2200505 450 001 9910678251903321 005 20230526113106.0 010 $a981-19-8551-0 024 7 $a10.1007/978-981-19-8551-5 035 $a(MiAaPQ)EBC7208088 035 $a(Au-PeEL)EBL7208088 035 $a(CKB)26189276000041 035 $a(DE-He213)978-981-19-8551-5 035 $a(PPN)269099182 035 $a(EXLCZ)9926189276000041 100 $a20230526d2023 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aBuilt-in fault-tolerant computing paradigm for resilient large-scale chip design $ea self-test, self-diagnosis, and self-repair-based approach /$fXiaowei Li, Guihai Yan, and Cheng Liu 205 $a1st ed. 2023. 210 1$aGateway East, Singapore :$cSpringer,$d[2023] 210 4$dİ2023 215 $a1 online resource (318 pages) 311 08$aPrint version: Li, Xiaowei Built-In Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design Singapore : Springer,c2023 9789811985508 320 $aIncludes bibliographical references and index. 327 $aChapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion. 330 $aWith the end of Dennard scaling and Moore?s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or ?3S? for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs. . 606 $aFault-tolerant computing 606 $aIntegrated circuits$xMasks$vCongresses 615 0$aFault-tolerant computing. 615 0$aIntegrated circuits$xMasks 676 $a004.2 700 $aLi$b Xiaowei$01345886 702 $aYan$b Guihai 702 $aLiu$b Cheng 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910678251903321 996 $aBuilt-in fault-tolerant computing paradigm for resilient large-scale chip design$93374622 997 $aUNINA