LEADER 02280nam 2200613Ia 450 001 9910454964103321 005 20200520144314.0 010 $a1-282-69464-2 010 $a9786612694646 010 $a0-262-25904-4 035 $a(CKB)1000000000816277 035 $a(OCoLC)646836717 035 $a(CaPaEBR)ebrary10335358 035 $a(SSID)ssj0000334865 035 $a(PQKBManifestationID)11929215 035 $a(PQKBTitleCode)TC0000334865 035 $a(PQKBWorkID)10271783 035 $a(PQKB)10861852 035 $a(MiAaPQ)EBC3339077 035 $a(OCoLC)471874683$z(OCoLC)646836717$z(OCoLC)709840916$z(OCoLC)710816884$z(OCoLC)743201396$z(OCoLC)743436496$z(OCoLC)748590913$z(OCoLC)813392442$z(OCoLC)816568700$z(OCoLC)961555332$z(OCoLC)962626421$z(OCoLC)988467094$z(OCoLC)991982884$z(OCoLC)1037930420$z(OCoLC)1038649041$z(OCoLC)1045494703$z(OCoLC)1055347278$z(OCoLC)1065100273$z(OCoLC)1081213290 035 $a(OCoLC-P)471874683 035 $a(MaCbMITP)7811 035 $a(Au-PeEL)EBL3339077 035 $a(CaPaEBR)ebr10335358 035 $a(CaONFJC)MIL269464 035 $a(OCoLC)471874683 035 $a(EXLCZ)991000000000816277 100 $a20081208d2009 uy 0 101 0 $aeng 135 $aurcn||||||||| 181 $ctxt 182 $cc 183 $acr 200 00$aArt school$b[electronic resource] $e(propositions for the 21st century) /$fedited and with an introduction by Steven Henry Madoff 210 $aCambridge, Mass. $cMIT Press$d2009 215 $a1 online resource (386 p.) 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a0-262-13493-4 320 $aIncludes bibliographical references and index. 330 $aLeading international artists and art educators consider the challenges of art education in today's dramatically changed art world. 606 $aArt$xStudy and teaching$xHistory$y21st century 606 $aEducation 608 $aElectronic books. 615 0$aArt$xStudy and teaching$xHistory 615 0$aEducation. 676 $a707.1 701 $aMadoff$b Steven Henry$01034445 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910454964103321 996 $aArt school$92453601 997 $aUNINA LEADER 04079nam 22005895 450 001 9910678251903321 005 20251009075046.0 010 $a981-19-8551-0 024 7 $a10.1007/978-981-19-8551-5 035 $a(MiAaPQ)EBC7208088 035 $a(Au-PeEL)EBL7208088 035 $a(CKB)26189276000041 035 $a(DE-He213)978-981-19-8551-5 035 $a(PPN)269099182 035 $a(EXLCZ)9926189276000041 100 $a20230301d2023 u| 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design $eA Self-Test, Self-Diagnosis, and Self-Repair-Based Approach /$fby Xiaowei Li, Guihai Yan, Cheng Liu 205 $a1st ed. 2023. 210 1$aSingapore :$cSpringer Nature Singapore :$cImprint: Springer,$d2023. 215 $a1 online resource (318 pages) 311 08$aPrint version: Li, Xiaowei Built-In Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design Singapore : Springer,c2023 9789811985508 320 $aIncludes bibliographical references and index. 327 $aChapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion. 330 $aWith the end of Dennard scaling and Moore?s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or ?3S? for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs. . 606 $aComputers 606 $aMicroprocessors 606 $aComputer architecture 606 $aHardware Performance and Reliability 606 $aComputer Hardware 606 $aProcessor Architectures 615 0$aComputers. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 14$aHardware Performance and Reliability. 615 24$aComputer Hardware. 615 24$aProcessor Architectures. 676 $a004.2 700 $aLi$b Xiaowei$01345886 702 $aYan$b Guihai 702 $aLiu$b Cheng 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910678251903321 996 $aBuilt-in fault-tolerant computing paradigm for resilient large-scale chip design$93374622 997 $aUNINA