LEADER 01641nam0-2200529---450- 001 990000064090203316 005 20000512 010 $a88-8149-150-8 035 $a0006409 035 $aUSA010006409 035 $a(ALEPH)000006409USA01 035 $a0006409 100 $a20000512d1999----|||y0itay0103----ba 101 0 $aita 102 $aIT 105 $a||||||||001yy 200 1 $a<> MUD e la gestione dei rifiuti$eil Modello Unico di dichiarazione ambientale$eistruzioni e modalità di compilazione$fFrancesco Marchello 210 $aNapoli$cFinanze & Lavoro$dcopyr. 1999 225 2 $aEdilizia & Territorio$v506 410 0$a12001$aEdilizia e Territorio 610 $aRifiuti Gestione Legislazione 610 $aRifiuti Gestione Manuali 676 $a346. 45044 700 1$aMARCHELLO,$bFrancesco$0416857 801 $aIT$bSALBC$gISBD 912 $a990000064090203316 951 $a346. 45044 MAR$b13839 Ing.$c346. 45044$d00000861 959 $aBK 979 $c20000914$lUSA01$h1729 979 $c20000919$lUSA01$h1047 979 $c20000919$lUSA01$h1521 979 $c20001019$lUSA01$h1055 979 $c20001019$lUSA01$h1453 979 $c20001019$lUSA01$h1500 979 $c20001019$lUSA01$h1538 979 $c20001024$lUSA01$h1514 979 $c20001027$lUSA01$h1518 979 $c20001027$lUSA01$h1522 979 $c20001110$lUSA01$h1709 979 $c20001124$lUSA01$h1207 979 $c20020403$lUSA01$h1614 979 $aPATRY$b90$c20040406$lUSA01$h1605 996 $aMUD e la gestione dei rifiuti$91490157 997 $aUNISA DB $aUSA01 SYS ID$a6409 bas $atec LEADER 01387nam 2200421 450 001 9910672188603321 005 20201104122341.0 010 $a84-947252-1-1 035 $a(CKB)4100000009605822 035 $a(MiAaPQ)EBC6771716 035 $a(OCoLC)1204299624 035 $a(FINmELB)ELB122571 035 $a(EXLCZ)994100000009605822 100 $a20201104d2017 uy 0 101 0 $aspa 135 $aurcnu|||||||| 181 $ctxt$2rdacontent/spa 182 $cc$2rdamedia/spa 183 $acr$2rdacarrier/spa 200 13$aLa prueba en el proceso penal $ea la luz de la jurisprudencia del Tribunal Supremo, Tribunal Constitucional y Tribunal Europeo de Derechos Humanos /$fSalud de Aguilar Gualda 210 1$a[Barcelona] :$cJ.M. Bosch Editor,$d2017. 215 $a1 recurso en li?nea (126 pa?ginas) 225 0 $aColeccio?n procesal ;$v54 311 $a84-947252-0-3 320 $aBibliografi?a: pa?ginas 125-126. 606 $aPruebas (Derecho penal)$zEspan?a 606 $aEvidence, Criminal$zSpain 608 $aLibros electronicos. 615 4$aPruebas (Derecho penal) 615 0$aEvidence, Criminal 676 $a345.4606 700 $aAguilar Gualda$b Salud de$01334471 801 0$bFINmELB 801 1$bFINmELB 906 $aBOOK 912 $a9910672188603321 996 $aLa prueba en el proceso penal$93046180 997 $aUNINA LEADER 09083nam 22008055 450 001 996465886003316 005 20231220142112.0 010 $a3-540-40058-3 024 7 $a10.1007/11859802 035 $a(CKB)1000000000283701 035 $a(SSID)ssj0000315794 035 $a(PQKBManifestationID)11215202 035 $a(PQKBTitleCode)TC0000315794 035 $a(PQKBWorkID)10255231 035 $a(PQKB)10362367 035 $a(DE-He213)978-3-540-40058-5 035 $a(MiAaPQ)EBC3068033 035 $a(PPN)123138116 035 $a(EXLCZ)991000000000283701 100 $a20100301d2006 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aAdvances in Computer Systems Architecture$b[electronic resource] $e11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings /$fedited by Chris Jesshope, Colin Egan 205 $a1st ed. 2006. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2006. 215 $a1 online resource (XIV, 605 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4186 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-40056-7 320 $aIncludes bibliographical references and index. 327 $aThe Era of Multi-core Chips -A Fresh Look on Software Challenges -- Streaming Networks for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential Functions for Large FPGAs -- Using Branch Prediction Information for Near-Optimal I-Cache Leakage -- Scientific Computing Applications on the Imagine Stream Processor -- Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination -- A Study of the Performance Potential for Dynamic Instruction Hints Selection -- Reorganizing UNIX for Reliability -- Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing -- Processor Directed Dynamic Page Policy -- Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications -- A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions -- ?TC ? An Intermediate Language for Programming Chip Multiprocessors -- Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays -- Trace-Based Data Cache Leakage Reduction at Link Time -- Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors -- Overload Protection for Commodity Network Appliances -- An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit -- A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster -- Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor -- Combining Wireless Sensor Network with Grid for Intelligent City Traffic -- A Novel Processor Architecture for Real-Time Control -- A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations -- Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs -- Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks -- Design of an Efficient Flexible Architecture for Color Image Enhancement -- Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three -- PMPS(3): A Performance Model of Parallel Systems -- Issues and Support for Dynamic Register Allocation -- A Heterogeneous Multi-core Processor Architecture for High Performance Computing -- Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation -- Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes -- Constructing Node-Disjoint Paths in Enhanced Pyramid Networks -- Striping Cache: A Global Cache for Striped Network File System -- DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing -- The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier -- Live Range Aware Cache Architecture -- The Challenges of Efficient Code-Generation for Massively Parallel Architectures -- Reliable Systolic Computing Through Redundancy -- A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks -- A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling -- On the Reliability of Drowsy Instruction Caches -- Design of a Reconfigurable Cryptographic Engine -- Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors -- The New BCD Subtractor and Its Reversible Logic Implementation -- Power-Efficient Microkernel of Embedded Operating System on Chip -- Understanding Prediction Limits Through Unbiased Branches -- Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP -- Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks -- Cycle Period Analysis and Optimization of Timed Circuits -- Acceleration Techniques for Chip-Multiprocessor Simulator Debug -- A DDL?Based Software Architecture Model -- Branch Behavior Characterization for Multimedia Applications -- Optimization and Evaluating of StreamYGX2 on MASA Stream Processor -- SecureTorrent: A Security Framework for File Swarming -- Register Allocation on Stream Processor with Local Register File -- A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance -- Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture -- Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining -- Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications -- Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols -- An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors -- An Efficient Approach to Energy Saving in Microcontrollers. 330 $aOn behalf of all of the people involved in the program selection, the program committee members as well as numerous other reviewers, we are both relieved and pleased to present you with the proceedings of the 2006 Asia-Pacific Computer Systems Architecture Conference (ACSAC 2006), which is being hosted in Shanghai on September 6?8, 2006. This is the 11th in a series of conferences, which started life in Australia, as the computer architecture component of the Australian Computer Science Week. In 1999 it ventured away from its roots for the first time, and the fourth Australasian Computer Architecture Conference was held in the beautiful city of Sails (Auckland, New Zealand). Perhaps it was because of a lack of any other computer architecture conference in Asia or just the attraction of traveling to the Southern Hemisphere but the conference became increasingly international during the subsequent three years and also changed its name to include Computer Systems Architecture, reflecting more the scope of the conference, which embraces both architectural and systems issues. In 2003, the conference again ventured offshore to reflect its constituency and since then has been held in Japan in the beautiful city of Aizu-Wakamatsu, followed by Beijing and Singapore. This year it again returns to China and next year will move to Korea for the first time, where it will be organized by the Korea University. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4186 606 $aComputer systems 606 $aComputer arithmetic and logic units 606 $aComputer input-output equipment 606 $aLogic design 606 $aComputer networks 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer System Implementation 606 $aArithmetic and Logic Structures 606 $aInput/Output and Data Communications 606 $aLogic Design 606 $aComputer Communication Networks 606 $aProcessor Architectures 615 0$aComputer systems. 615 0$aComputer arithmetic and logic units. 615 0$aComputer input-output equipment. 615 0$aLogic design. 615 0$aComputer networks. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 14$aComputer System Implementation. 615 24$aArithmetic and Logic Structures. 615 24$aInput/Output and Data Communications. 615 24$aLogic Design. 615 24$aComputer Communication Networks. 615 24$aProcessor Architectures. 676 $a004.2/2 702 $aJesshope$b Chris$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aEgan$b Colin$f1956-$4edt$4http://id.loc.gov/vocabulary/relators/edt 712 12$aACSAC (Asia-Pacific Computer Systems Architecture Conference) 906 $aBOOK 912 $a996465886003316 996 $aAdvances in Computer Systems Architecture$9772404 997 $aUNISA