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[et al.] 210 $aNew York $cSpringer$d2012 215 $a1 online resource (258 p.) 300 $aDescription based upon print version of record. 311 $a1-4614-1358-3 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- Modeling and Specification of SoC Designs -- Automated Generation of Directed Tests -- Functional Test Compaction.- Property Clustering and Learning Techniques -- Decision Ordering Based Learning Techniques -- Synchronized Generation of Directed Tests -- Learning-Oriented Property Decomposition Approaches -- Directed Test Generation for Multicore Architectures -- Test Generation for Cache Coherence Validation.- Reuse of System-Level Tests for Implementation Validation -- Conclusion. 330 $aThis book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures.  Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions.  The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost. 606 $aInformation resources management 606 $aInformation technology 615 0$aInformation resources management. 615 0$aInformation technology. 676 $a003.3 700 $aChen$b Mingsong$01060861 701 $aBlasch$b Erik$0986166 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910437760703321 996 $aSystem-level validation$92515972 997 $aUNINA