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101 0 $aeng
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181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 00$aEmbedded and fan-out wafer and panel level packaging technologies for advanced application spaces $ehigh performance compute and system-in-package /$fedited by Beth Keser and Steffen Kro?hnert
210  1$aPiscataway, New Jersey ;$aHoboken, New Jersey :$cIEEE Press :$cWiley,$d[2022]
210  4$dİ2022
215   $a1 online resource (323 pages)
225 1 $aIEEE Press Ser.
311 08$aPrint version: Keser, Beth Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces Newark : John Wiley & Sons, Incorporated,c2022 9781119793779 
320   $aIncludes bibliographical references and index.
410  0$aIEEE Press Ser.
606   $aChip scale packaging
606   $aIntegrated circuits$xWafer-scale integration
606   $aMicroelectronics
615  0$aChip scale packaging.
615  0$aIntegrated circuits$xWafer-scale integration.
615  0$aMicroelectronics.
676   $a621.395
702   $aKeser$b Beth$f1971-
702   $aKroehnert$b Steffen$f1970-
801  0$bMiAaPQ
801  1$bMiAaPQ
801  2$bMiAaPQ
906   $aBOOK
912   $a9910555144103321
996   $aEmbedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces$92816245
997   $aUNINA