LEADER 03457nam 2200481 450 001 9910523003403321 005 20220415055747.0 010 $a3-030-79774-0 024 7 $a10.1007/978-3-030-79774-4 035 $a(CKB)4100000011994778 035 $a(DE-He213)978-3-030-79774-4 035 $a(MiAaPQ)EBC6689098 035 $a(Au-PeEL)EBL6689098 035 $a(PPN)257357165 035 $a(EXLCZ)994100000011994778 100 $a20220415d2022 uy 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aBlocks, towards energy-efficient, coarse-grained reconfigurable architectures /$fMark Wijtvliet, Henk Corporaal, Akash Kumar 205 $a1st ed. 2022. 210 1$aCham, Switzerland :$cSpringer,$d[2022] 210 4$dİ2022 215 $a1 online resource (X, 220 p. 158 illus., 117 illus. in color.) 311 $a3-030-79773-2 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- CGRA background -- Concept of the Blocks architecture -- The Blocks framework -- Energy, area, and performance evaluation -- Architectural model -- Case study: the BrainSense platform -- Conclusion. 330 $aThis book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals. Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs; Offers a new view on the positioning of CGRAs; Provides an in-depth description of structure of the Blocks CGRA and its unique aspects; Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches; Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model. 606 $aAdaptive computing systems 615 0$aAdaptive computing systems. 676 $a004 700 $aWijtvliet$b Mark$01078620 702 $aCorporaal$b Henk 702 $aKumar$b Akash 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910523003403321 996 $aBlocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures$92590822 997 $aUNINA