LEADER 03894nam 22005055 450 001 9910497109703321 005 20211006042709.0 010 $a3-030-79774-0 024 7 $a10.1007/978-3-030-79774-4 035 $a(CKB)4100000011994778 035 $a(DE-He213)978-3-030-79774-4 035 $a(MiAaPQ)EBC6689098 035 $a(Au-PeEL)EBL6689098 035 $a(EXLCZ)994100000011994778 100 $a20210802d2022 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aBlocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures $b[electronic resource] /$fby Mark Wijtvliet, Henk Corporaal, Akash Kumar 205 $a1st ed. 2022. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2022. 215 $a1 online resource (X, 220 p. 158 illus., 117 illus. in color.) 311 $a3-030-79773-2 327 $aIntroduction -- CGRA background -- Concept of the Blocks architecture -- The Blocks framework -- Energy, area, and performance evaluation -- Architectural model -- Case study: the BrainSense platform -- Conclusion. 330 $aThis book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals. Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs; Offers a new view on the positioning of CGRAs; Provides an in-depth description of structure of the Blocks CGRA and its unique aspects; Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches; Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model. 606 $aElectronic circuits 606 $aMicroprocessors 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 608 $aElectronic books. 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 676 $a621.3815 700 $aWijtvliet$b Mark$4aut$4http://id.loc.gov/vocabulary/relators/aut$0986847 702 $aCorporaal$b Henk$4aut$4http://id.loc.gov/vocabulary/relators/aut 702 $aKumar$b Akash$4aut$4http://id.loc.gov/vocabulary/relators/aut 801 0$bMiAaPQ 906 $aBOOK 912 $a9910497109703321 996 $aBlocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures$92255305 997 $aUNINA