LEADER 02682 am 2200577 n 450 001 9910495676603321 005 20240104030706.0 010 $a2-39061-046-3 035 $a(CKB)4100000011945183 035 $a(FrMaCLE)OB-pucl-7352 035 $a(PPN)256383324 035 $a(EXLCZ)994100000011945183 100 $a20210603j|||||||| ||| 0 101 0 $afre 135 $auu||||||m|||| 200 02$aL?annonce faite au lecteur$eLa circulation de l?information sur les livres en Europe (16e-18e siècles)$fAnnie Charon, Sabine Juratic, Isabelle Pantin 210 $aLouvain-la-Neuve$cPresses universitaires de Louvain$d2021 215 $a1 online resource (318 p.) 311 $a2-87558-509-6 330 $aL?information sur les livres disponibles a circulé sous de multiples formes dans l?Europe de l?Ancien Régime (correspondances, articles et comptes rendus dans les périodiques, projets de bibliothèques modèles, catalogues). Dans cette grande activité bibliographique, le souci d?annoncer les parutions se combinait souvent avec celui d?analyser, de juger, de dresser une topographie du monde des lettres. L?Annonce faite au lecteur explore ce domaine. Il s?intéresse à quelques grands acteurs de la mise en relation du monde des livres et du public des lecteurs, ainsi qu?aux supports de l?information et de la publicité. Il fait ressortir l?évolution qui a eu lieu entre Renaissance et Lumières avec l?adaptation des modes d?information aux attentes d?un lectorat disséminé dans toute l?Europe et de plus en plus diversifié. 606 $aLiterature 606 $alivre 606 $alittérature 606 $alectorat 606 $aEurope 615 4$aLiterature 615 4$alivre 615 4$alittérature 615 4$alectorat 615 4$aEurope 700 $aBas Martín$b Nicolás$01458230 701 $aBlair$b Ann$0259226 701 $aCavaillon Giomi$b Joan$01458231 701 $aChapron$b Emmanuelle$0472887 701 $aCharon$b Annie$01234178 701 $aChotard$b Françoise$01458232 701 $aFougerol$b Clara$01458233 701 $aJuratic$b Sabine$0163815 701 $aLatour$b Patrick$01454120 701 $aMcKenna$b Antony$0154041 701 $aNaud-Betteridge$b Mariette$01458234 701 $aPantin$b Isabelle$01286310 701 $aSarrazin$b Véronique$01281951 701 $aSimonin$b Charlotte$01297692 701 $aSomov$b Vladimir$01307239 701 $aVittu$b Jean-Pierre$01305550 801 0$bFR-FrMaCLE 906 $aBOOK 912 $a9910495676603321 996 $aL?annonce faite au lecteur$93658218 997 $aUNINA LEADER 04995nam 22008175 450 001 9910484142403321 005 20251226202535.0 010 $a3-642-36157-9 024 7 $a10.1007/978-3-642-36157-9 035 $a(CKB)3400000000102980 035 $a(SSID)ssj0000880021 035 $a(PQKBManifestationID)11509150 035 $a(PQKBTitleCode)TC0000880021 035 $a(PQKBWorkID)10873609 035 $a(PQKB)10409838 035 $a(DE-He213)978-3-642-36157-9 035 $a(MiAaPQ)EBC3068803 035 $a(PPN)168329840 035 $a(EXLCZ)993400000000102980 100 $a20130107d2013 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation $e22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers /$fedited by José L. Ayala, Delong Shang, Alex Yakovlev 205 $a1st ed. 2013. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2013. 215 $a1 online resource (IX, 258 p. 150 illus.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v7606 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a3-642-36156-0 320 $aIncludes bibliographical references and index. 327 $aSleep-Transistor Based Power-Gating Tradeoff Analyses -- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level -- Non-invasive Power Simulation at System-Level with SystemC -- A Standard Cell Optimization Method for Near-Threshold Voltage Operations -- An Extended Metastability Simulation Method for Synchronizer Characterization -- Phase Space Based NBTI Model -- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths -- Noise Margin Based Library Optimization Considering Variability in Sub-threshold -- TCP Window Based DVFS for Low Power Network Controller SoC -- A Generic Architecture for Robust Asynchronous Communication Links -- Direct Statistical Simulation of Timing Properties in Sequential Circuits -- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture -- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications -- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor -- Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation -- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines -- Dynamic Power Management of a Computer with Self Power-Managed Components -- Case Studies of Logical Computation on Stochastic Bit Streams. 330 $aThis book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v7606 606 $aElectronic digital computers$xEvaluation 606 $aComputer simulation 606 $aComputer networks 606 $aComputer hardware description languages 606 $aLogic design 606 $aCompilers (Computer programs) 606 $aSystem Performance and Evaluation 606 $aComputer Modelling 606 $aComputer Communication Networks 606 $aRegister-Transfer-Level Implementation 606 $aLogic Design 606 $aCompilers and Interpreters 615 0$aElectronic digital computers$xEvaluation. 615 0$aComputer simulation. 615 0$aComputer networks. 615 0$aComputer hardware description languages. 615 0$aLogic design. 615 0$aCompilers (Computer programs). 615 14$aSystem Performance and Evaluation. 615 24$aComputer Modelling. 615 24$aComputer Communication Networks. 615 24$aRegister-Transfer-Level Implementation. 615 24$aLogic Design. 615 24$aCompilers and Interpreters. 676 $a004.24 701 $aAyala$b Jose L$0980154 701 $aShang$b Delong$01755319 701 $aYakovlev$b Alex$01755320 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910484142403321 996 $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$94521104 997 $aUNINA