LEADER 06106nam 22008295 450 001 9910485047503321 005 20230224003151.0 010 $a3-540-78610-4 024 7 $a10.1007/978-3-540-78610-8 035 $a(CKB)1000000000490913 035 $a(SSID)ssj0000319781 035 $a(PQKBManifestationID)11265298 035 $a(PQKBTitleCode)TC0000319781 035 $a(PQKBWorkID)10343376 035 $a(PQKB)10169609 035 $a(DE-He213)978-3-540-78610-8 035 $a(MiAaPQ)EBC3063621 035 $a(MiAaPQ)EBC6386365 035 $a(PPN)128125314 035 $a(EXLCZ)991000000000490913 100 $a20100301d2008 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aReconfigurable Computing: Architectures, Tools, and Applications $e4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings /$fedited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz 205 $a1st ed. 2008. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2008. 215 $a1 online resource (XIV, 346 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4943 300 $aIncludes index. 311 $a3-540-78609-0 320 $aIncludes bibliographical references and index. 327 $aKeynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World?s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions ? A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware ? A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v4943 606 $aComputer science 606 $aComputers 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer networks 606 $aElectronic digital computers?Evaluation 606 $aComputer systems 606 $aTheory of Computation 606 $aComputer Hardware 606 $aProcessor Architectures 606 $aComputer Communication Networks 606 $aSystem Performance and Evaluation 606 $aComputer System Implementation 615 0$aComputer science. 615 0$aComputers. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer networks. 615 0$aElectronic digital computers?Evaluation. 615 0$aComputer systems. 615 14$aTheory of Computation. 615 24$aComputer Hardware. 615 24$aProcessor Architectures. 615 24$aComputer Communication Networks. 615 24$aSystem Performance and Evaluation. 615 24$aComputer System Implementation. 676 $a004 702 $aWoods$b Roger$f1963- 712 12$aARC (Symposium) 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bUtOrBLW 906 $aBOOK 912 $a9910485047503321 996 $aReconfigurable Computing: Architectures, Tools and Applications$9772428 997 $aUNINA