LEADER 08349nam 22008535 450 001 9910485025903321 005 20230223060144.0 010 $a3-540-95948-3 024 7 $a10.1007/978-3-540-95948-9 035 $a(CKB)1000000000575766 035 $a(SSID)ssj0000318341 035 $a(PQKBManifestationID)11226186 035 $a(PQKBTitleCode)TC0000318341 035 $a(PQKBWorkID)10307543 035 $a(PQKB)11444973 035 $a(DE-He213)978-3-540-95948-9 035 $a(MiAaPQ)EBC3063922 035 $a(PPN)132870762 035 $a(EXLCZ)991000000000575766 100 $a20100301d2009 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$b[electronic resource] $e18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers /$fedited by Lars Svensson, José Monteiro 205 $a1st ed. 2009. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2009. 215 $a1 online resource (XIII, 462 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5349 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-540-95947-5 320 $aIncludes bibliographical references and index. 327 $aSession 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope. 330 $aThis book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5349 606 $aLogic design 606 $aMicroprocessors 606 $aComputer architecture 606 $aElectronic digital computers?Evaluation 606 $aComputer arithmetic and logic units 606 $aComputer storage devices 606 $aMemory management (Computer science) 606 $aElectronic circuits 606 $aLogic Design 606 $aProcessor Architectures 606 $aSystem Performance and Evaluation 606 $aArithmetic and Logic Structures 606 $aComputer Memory Structure 606 $aElectronic Circuits and Systems 615 0$aLogic design. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aElectronic digital computers?Evaluation. 615 0$aComputer arithmetic and logic units. 615 0$aComputer storage devices. 615 0$aMemory management (Computer science). 615 0$aElectronic circuits. 615 14$aLogic Design. 615 24$aProcessor Architectures. 615 24$aSystem Performance and Evaluation. 615 24$aArithmetic and Logic Structures. 615 24$aComputer Memory Structure. 615 24$aElectronic Circuits and Systems. 676 $a620/.004202825536 686 $aDAT 190f$2stub 686 $aELT 272f$2stub 686 $aSS 4800$2rvk 702 $aSvensson$b Lars$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aMonteiro$b José$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a9910485025903321 996 $aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation$9772134 997 $aUNINA