LEADER 05110nam 2200637Ia 450 001 9910484851603321 005 20200520144314.0 010 $a1-280-38556-1 010 $a9786613563484 010 $a3-642-11515-2 024 7 $a10.1007/978-3-642-11515-8 035 $a(CKB)2670000000003390 035 $a(SSID)ssj0000399487 035 $a(PQKBManifestationID)11279226 035 $a(PQKBTitleCode)TC0000399487 035 $a(PQKBWorkID)10376499 035 $a(PQKB)11610456 035 $a(DE-He213)978-3-642-11515-8 035 $a(MiAaPQ)EBC3064980 035 $a(PPN)149057075 035 $a(EXLCZ)992670000000003390 100 $a20091208d2010 uy 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aHigh Performance Embedded Architectures and Compilers $e5th International Conference, HIPEAC 2010 ; Pisa, Italy, January 25-27, 2010 ; proceedings /$fYale N. Patt, ... [et al.] ; (eds.) 205 $a1st ed. 2010. 210 $aBerlin $cSpringer$d2010 215 $a1 online resource (XIII, 370 p.) 225 1 $aLecture notes in computer science,$x0302-9743 ;$v5952 225 1 $aLNCS sublibrary. SL 1, Theoretical computer science and general issues 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-642-11514-4 320 $aIncludes bibliographical references and index. 327 $aInvited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload ? Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. 330 $aThis book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators. 410 0$aLecture notes in computer science ;$v5952. 410 0$aLNCS sublibrary.$nSL 1,$pTheoretical computer science and general issues. 517 3 $aHiPEAC 2010 606 $aCompilers (Computer programs)$vCongresses 606 $aComputer architecture$vCongresses 606 $aEmbedded computer systems$vCongresses 615 0$aCompilers (Computer programs) 615 0$aComputer architecture 615 0$aEmbedded computer systems 676 $a005.4/53 712 12$aHiPEAC 2010 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910484851603321 996 $aHigh Performance Embedded Architectures and Compilers$9772079 997 $aUNINA