LEADER 06089nam 2200649 a 450 001 9910484844303321 005 20200520144314.0 010 $a1-280-38685-1 010 $a9786613564771 010 $a3-642-13374-6 024 7 $a10.1007/978-3-642-13374-9 035 $a(CKB)2670000000028958 035 $a(SSID)ssj0000446587 035 $a(PQKBManifestationID)11285494 035 $a(PQKBTitleCode)TC0000446587 035 $a(PQKBWorkID)10511797 035 $a(PQKB)10422311 035 $a(DE-He213)978-3-642-13374-9 035 $a(MiAaPQ)EBC3065371 035 $a(PPN)14906358X 035 $a(EXLCZ)992670000000028958 100 $a20100423d2010 uy 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aLanguages and compilers for parallel computing $e22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, revised selected papers /$f[edited by] Guang R. Gao ... [et al] 205 $a1st ed. 210 $aNew York $cSpringer$d2010 215 $a1 online resource (XI, 426 p. 186 illus.) 225 1 $aLecture notes in computer science,$x0302-9743 ;$v5898 225 1 $aLNCS sublibrary. SL 1, Theoretical computer science and general issues 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-642-13373-8 320 $aIncludes bibliographical references and index. 327 $aA Communication Framework for Fault-Tolerant Parallel Execution -- The STAPL pList -- Hardware Support for OpenMP Collective Operations -- Loop Transformation Recipes for Code Generation and Auto-Tuning -- MIMD Interpretation on a GPU -- TL-DAE: Thread-Level Decoupled Access/Execution for OpenMP on the Cyclops-64 Many-Core Processor -- Mapping Streaming Languages to General Purpose Processors through Vectorization -- A Balanced Approach to Application Performance Tuning -- Automatically Tuning Parallel and Parallelized Programs -- DFT Performance Prediction in FFTW -- Safe and Familiar Multi-core Programming by Means of a Hybrid Functional and Imperative Language -- Hierarchical Place Trees: A Portable Abstraction for Task Parallelism and Data Movement -- OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers -- Programming with Intervals -- Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories -- Synchronization-Free Automatic Parallelization: Beyond Affine Iteration-Space Slicing -- Automatic Data Distribution for Improving Data Locality on the Cell BE Architecture -- Automatic Restructuring of Linked Data Structures -- Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops -- Efficient Tiled Loop Generation: D-Tiling -- Effective Source-to-Source Outlining to Support Whole Program Empirical Optimization -- Speculative Optimizations for Parallel Programs on Multicores -- Fastpath Speculative Parallelization -- PSnAP: Accurate Synthetic Address Streams through Memory Profiles -- Enforcing Textual Alignment of Collectives Using Dynamic Checks -- A Code Generation Approach for Auto-Vectorization in the Spade Compiler -- Portable Just-in-Time Specialization of Dynamically Typed Scripting Languages -- Reducing Training Time in a One-Shot Machine Learning-Based Compiler -- Optimizing Local Memory Allocation and Assignment through a Decoupled Approach -- Unrolling Loops Containing Task Parallelism. 330 $aItisourpleasuretopresentthepapersacceptedforthe22ndInternationalWo- shop on Languages and Compilers for Parallel Computing held during October 8?10 2009 in Newark Delaware, USA. Since 1986, LCPC has became a valuable venueforresearchersto reportonworkinthegeneralareaofparallelcomputing, high-performance computer architecture and compilers. LCPC 2009 continued this tradition and in particular extended the area of interest to new parallel computing accelerators such as the IBM Cell Processor and Graphic Processing Unit (GPU). This year we received 52 submissions from 15 countries. Each submission receivedatleastthreereviewsandmosthadfour.ThePCalsosoughtadditional externalreviewsforcontentiouspapers.ThePCheldanall-dayphoneconference on August 24 to discuss the papers. PC members who had a con?ict of interest were asked to leave the call temporarily when the corresponding papers were discussed. From the 52 submissions, the PC selected 25 full papers and 5 short paperstobeincludedintheworkshopproceeding,representinga58%acceptance rate. We were fortunate to have three keynote speeches, a panel discussion and a tutorial in this year?s workshop. First, Thomas Sterling, Professor of Computer Science at Louisiana State University, gave a keynote talk titled ?HPC in Phase Change: Towards a New Parallel Execution Model.? Sterling argued that a new multi-dimensional research thrust was required to realize the design goals with regard to power, complexity, clock rate and reliability in the new parallel c- puter systems.ParalleX,anexploratoryexecutionmodeldevelopedbySterling?s group was introduced to guide the co-design of new architectures, programming methods and system software. 410 0$aLecture notes in computer science ;$v5898. 410 0$aLNCS sublibrary.$nSL 1,$pTheoretical computer science and general issues. 517 3 $aLCPC 2009 606 $aParallel processing (Electronic computers)$vCongresses 606 $aProgramming languages (Electronic computers)$vCongresses 606 $aCompilers (Computer programs)$vCongresses 615 0$aParallel processing (Electronic computers) 615 0$aProgramming languages (Electronic computers) 615 0$aCompilers (Computer programs) 676 $a005.13 701 $aGao$b Guang R$052946 712 12$aWorkshop on Languages and Compilers for Parallel Computing 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910484844303321 996 $aLanguages and compilers for parallel computing$94203324 997 $aUNINA