LEADER 06939nam 22007695 450 001 9910484686403321 005 20200703055850.0 010 $a3-319-02444-2 024 7 $a10.1007/978-3-319-02444-8 035 $a(CKB)3710000000015829 035 $a(SSID)ssj0000988045 035 $a(PQKBManifestationID)11534987 035 $a(PQKBTitleCode)TC0000988045 035 $a(PQKBWorkID)10949801 035 $a(PQKB)10828442 035 $a(DE-He213)978-3-319-02444-8 035 $a(MiAaPQ)EBC3107100 035 $a(PPN)172424674 035 $a(EXLCZ)993710000000015829 100 $a20130829d2013 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aAutomated Technology for Verification and Analysis $e11th International Symposium, ATVA 2013, Hanoi, Vietnam, October 15-18, 2013, Proceedings /$fedited by Dang Van Hung, Mizuhito Ogawa 205 $a1st ed. 2013. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2013. 215 $a1 online resource (XIV, 528 p. 115 illus.) 225 1 $aProgramming and Software Engineering ;$v8172 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a3-319-02443-4 327 $aInvited Papers.-Acceleration for Petri Nets -- Automated Verification and Strategy Synthesis for Probabilistic Systems -- SMT-Based Software Model Checking: Explicit Scheduler, Symbolic Threads -- Regular Papers.-Effective Translation of LTL to Deterministic Rabin Automata: Beyond the (F,G)-Fragment -- Improved Upper and Lower Bounds for Bšuchi Disambiguation -- Time-Bounded Reachability for Monotonic Hybrid Automata: Complexity and Fixed Points -- An Automatic Technique for Checking the Simulation of Timed Systems -- Synthesis of Bounded Integer Parameters for Parametric Timed Reachability Games -- Kleene Algebras and Semimodules for Energy Problems -- Looking at Mean-Payoff and Total-Payoff through Windows -- Weighted Safety -- A Framework for Ranking Vacuity Results -- Synthesizing Masking Fault-Tolerant Systems from Deontic Specifications -- Verification of a Dynamic Management Protocol for Cloud Applications -- Compact Symbolic Execution -- Multi-threaded Explicit State Space Exploration with State Reconstruction -- Verification of Heap Manipulating Programs with Ordered Data by Extended Forest Automata -- Integrating Policy Iterations in Abstract Interpreters -- Interpolation Properties and SAT-Based Model Checking -- Analysis of Message Passing Programs Using SMT-Solvers -- An Expressive Framework for Verifying Deadlock Freedom -- Expected Termination Time in BPA Games -- Precise Cost Analysis via Local Reasoning -- Control Flow Refinement and Symbolic Computation of Average Case Bound -- Termination and Cost Analysis of Loops with Concurrent Interleavings -- Linear Ranking for Linear Lasso Programs -- Merge and Conquer: State Merging in Parametric Timed Automata -- An Automata-Theoretic Approach to Reasoning about Parameterized Systems and Specifications -- Pushdown Systems with Stack Manipulation -- Robustness Analysis of String Transducers -- Tool Papers -- Manipulating LTL Formulas Using Spot 1.0 -- Rabinizer 2: Small Deterministic Automata for LTL\GU -- LTL Model Checking with Neco -- Solving Parity Games on the GPU -- PyEcdar: Towards Open Source Implementation for Timed Systems -- CCMC: A Conditional CSL Model Checker for Continuous-Time Markov Chains -- NLTOOLBOX: A Library for Reachability Computation of Nonlinear Dynamical Systems -- CELL: A Compositional Verification Framework -- VCS: A Verifier for Component-Based Systems -- SmacC: A Retargetable Symbolic Execution Engine -- MoTraS: A Tool for Modal Transition Systems and Their Extensions -- Cunf: A Tool for Unfolding and Verifying Petri Nets with Read Arcs -- Short Papers -- SAT Based Verification of Network Data Planes -- A Theory for Control-Flow Graph Exploration -- The Quest for Precision: A Layered Approach for Data Race Detection in Static Analysis. 330 $aThis book constitutes the refereed proceedings of the 11th International Symposium on Automated Technology for Verification and Analysis, ATVA 2013, held at Hanoi, Vietnam, in October 2013. The 27 regular papers, 3 short papers and 12 tool papers presented together with 3  invited talks were carefully selected from73 submissions. The papers are organized in topical, sections on analysis and verification of hardware circuits, systems-on-chip and embedded systems, analysis of real-time, hybrid, priced/weighted and probabilistic systems, deductive, algorithmic, compositional, and abstraction/refinement techniques for analysis and verification, analytical techniques for safety, security, and dependability, testing and runtime analysis based on verification technology, analysis and verification of parallel and concurrent hardware/software systems, verification in industrial practice, and applications and case studies. 410 0$aProgramming and Software Engineering ;$v8172 606 $aSoftware engineering 606 $aComputer programming 606 $aComputer communication systems 606 $aComputer logic 606 $aProgramming languages (Electronic computers) 606 $aSoftware Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/I14029 606 $aProgramming Techniques$3https://scigraph.springernature.com/ontologies/product-market-codes/I14010 606 $aComputer Communication Networks$3https://scigraph.springernature.com/ontologies/product-market-codes/I13022 606 $aLogics and Meanings of Programs$3https://scigraph.springernature.com/ontologies/product-market-codes/I1603X 606 $aProgramming Languages, Compilers, Interpreters$3https://scigraph.springernature.com/ontologies/product-market-codes/I14037 606 $aSoftware Engineering/Programming and Operating Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/I14002 615 0$aSoftware engineering. 615 0$aComputer programming. 615 0$aComputer communication systems. 615 0$aComputer logic. 615 0$aProgramming languages (Electronic computers). 615 14$aSoftware Engineering. 615 24$aProgramming Techniques. 615 24$aComputer Communication Networks. 615 24$aLogics and Meanings of Programs. 615 24$aProgramming Languages, Compilers, Interpreters. 615 24$aSoftware Engineering/Programming and Operating Systems. 676 $a004.015113 702 $aVan Hung$b Dang$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aOgawa$b Mizuhito$4edt$4http://id.loc.gov/vocabulary/relators/edt 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910484686403321 996 $aAutomated Technology for Verification and Analysis$9772478 997 $aUNINA