LEADER 01127nam0-22003851i-450- 001 990003100490403321 005 20131121100823.0 035 $a000310049 035 $aFED01000310049 035 $a(Aleph)000310049FED01 035 $a000310049 100 $a20030910d1981----km-y0itay50------ba 101 0 $aita 102 $aIT 200 1 $aIndustrializzazione, multinazionali e dipendenza tecnologica$eL'esperienza dei paesi arabi esportatori di petrolio$fGiovanni Balcet. 210 $aTorino$cLoescher$d1981. 215 $a211 p.$d20 cm 225 1 $aLoescher universitā 610 0 $aInnovazioni tecnologiche$aAspetti economici 610 0 $aMultinazionali 610 0 $aPaesi arabi 610 0 $aPetrolio 676 $aF/1.351 676 $aH/2.2214 676 $aO/1.22 702 1$aBalcet,$bGiovanni 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990003100490403321 952 $aISVE O1-O2.231$fDECTS 952 $aO/112 BAL$b11110/I$fSES 959 $aDECTS 959 $aSES 996 $aIndustrializzazione, multinazionali e dipendenza tecnologica$9459597 997 $aUNINA LEADER 01645nam 2200433 n 450 001 996384741103316 005 20200818213443.0 035 $a(CKB)4940000000067225 035 $a(EEBO)2240913679 035 $a(UnM)99841408e 035 $a(UnM)99841408 035 $a(EXLCZ)994940000000067225 100 $a19910401d1638 uy | 101 0 $aeng 135 $aurbn||||a|bb| 200 10$aReasons against the rendering of our sworne and subscribed confession of faith$b[electronic resource] 210 $a[Edinburgh $cPrinted by G. Anderson?$d1638] 215 $a[4] p 300 $aBy Archibald Johnston, Lord Warriston. Erroneously attributed to Alexander Henderson. 300 $aCaption title. 300 $aImprint from STC. 300 $aSignatures: Cē . 300 $aIn this edition C2r line 1 has: prelates. 300 $aProbably intended to be issued with STC 22026, but often found bound with STC 22030, 22056, and other items (STC). 300 $aIdentified as STC 22036a on UMI microfilm. 300 $aReproduction of the original in the Folger Shakespeare Library. 330 $aeebo-0055 606 $aCovenants (Church polity)$vEarly works to 1800 607 $aScotland$xChurch history$y17th century$vEarly works to 1800 615 0$aCovenants (Church polity) 700 $aWarriston$b Archibald Johnston$cLord,$f1611-1663.$01001116 801 0$bCu-RivES 801 1$bCu-RivES 801 2$bCStRLIN 801 2$bWaOLN 906 $aBOOK 912 $a996384741103316 996 $aReasons against the rendering of our sworne and subscribed confession of faith$92340730 997 $aUNISA LEADER 06562nam 22008295 450 001 9910484388603321 005 20251226203326.0 010 $a1-282-33186-8 010 $a9786612331862 010 $a3-642-03138-2 024 7 $a10.1007/978-3-642-03138-0 035 $a(CKB)1000000000761238 035 $a(EBL)450443 035 $a(OCoLC)437345750 035 $a(SSID)ssj0000294990 035 $a(PQKBManifestationID)11227336 035 $a(PQKBTitleCode)TC0000294990 035 $a(PQKBWorkID)10312698 035 $a(PQKB)11360098 035 $a(DE-He213)978-3-642-03138-0 035 $a(MiAaPQ)EBC450443 035 $a(MiAaPQ)EBC6416137 035 $a(PPN)136310788 035 $a(EXLCZ)991000000000761238 100 $a20100301d2009 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aEmbedded Computer Systems: Architectures, Modeling, and Simulation $e9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings /$fedited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong 205 $a1st ed. 2009. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2009. 215 $a1 online resource (354 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5657 300 $aDescription based upon print version of record. 311 08$a3-642-03137-4 320 $aIncludes bibliographical references and index. 327 $aBeachnote -- What Else Is Broken? Can We Fix It? -- Architectures for Multimedia -- Programmable and Scalable Architecture for Graphics Processing Units -- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors -- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey -- Programmable Accelerators for Reconfigurable Video Decoder -- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study -- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks -- Multi/Many Cores Architectures -- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC -- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture -- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management -- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA -- VLSI Architectures Design -- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing -- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata -- Prediction in Dynamic SDRAM Controller Policies -- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI -- Architecture Modeling and Exploration Tools -- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration -- Modeling Scalable SIMD DSPs in LISA -- NoGAP: A Micro Architecture Construction Framework -- A Comparison of NoTA and GENESYS -- Special Session 1: Instruction-Set Customization -- to Instruction-Set Customization -- Constraint-Driven Identification of Application Specific Instructions in the DURASE System -- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) -- Runtime Adaptive Extensible Embedded Processors ? A Survey -- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures -- to the Future of Reconfigurable Computing and Processor Architectures -- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems -- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study -- Reconfigurable Multicore Server Processors for Low Power Operation -- Reconfigurable Computing in the New Age of Parallelism -- Reconfigurable Multithreading Architectures: A Survey -- Special Session 3: Mastering Cell BE and GPU Execution Platforms -- to Mastering Cell BE and GPU Execution Platforms -- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors -- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs -- Experiences with Cell-BE and GPU for Tomography -- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell -- Exploiting Locality on the Cell/B.E. through Bypassing -- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System. 330 $aThis book constitutes the refereed proceedings of the 9th International Workshop on Architectures, Modeling, and Simulation, SAMOS 2009, held on Samos, Greece, on July 20-23, 2009. The 18 regular papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in topical sections on architectures for multimedia, multi/many cores architectures, VLSI architectures design, architecture modeling and exploration tools. In addition there are 14 papers from three special sessions which were organized on topics of current interest: instruction-set customization, reconfigurable computing and processor architectures, and mastering cell BE and GPU execution platforms. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5657 606 $aComputer systems 606 $aComputers 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer networks 606 $aElectronic digital computers$xEvaluation 606 $aComputer System Implementation 606 $aComputer Hardware 606 $aProcessor Architectures 606 $aComputer Communication Networks 606 $aSystem Performance and Evaluation 615 0$aComputer systems. 615 0$aComputers. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer networks. 615 0$aElectronic digital computers$xEvaluation. 615 14$aComputer System Implementation. 615 24$aComputer Hardware. 615 24$aProcessor Architectures. 615 24$aComputer Communication Networks. 615 24$aSystem Performance and Evaluation. 676 $a004.22 702 $aBertels$b Koen 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910484388603321 996 $aEmbedded Computer Systems: Architectures, Modeling, and Simulation$9772127 997 $aUNINA