LEADER 06718nam 22008775 450 001 9910483949703321 005 20230330005320.0 010 $a3-319-30695-2 024 7 $a10.1007/978-3-319-30695-7 035 $a(CKB)3710000000627347 035 $a(SSID)ssj0001657038 035 $a(PQKBManifestationID)16438116 035 $a(PQKBTitleCode)TC0001657038 035 $a(PQKBWorkID)14988912 035 $a(PQKB)11440836 035 $a(DE-He213)978-3-319-30695-7 035 $a(MiAaPQ)EBC6298692 035 $a(MiAaPQ)EBC5594581 035 $a(Au-PeEL)EBL5594581 035 $a(OCoLC)946038062 035 $a(PPN)192771760 035 $a(EXLCZ)993710000000627347 100 $a20160330d2016 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aArchitecture of Computing Systems -- ARCS 2016 $e29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings /$fedited by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich 205 $a1st ed. 2016. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2016. 215 $a1 online resource (XX, 402 p. 164 illus.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v9637 300 $aIncludes index. 311 $a3-319-30694-4 327 $aConfigurable and In-Memory Accelerators -- Towards Multicore Performance with Configurable Computing Units -- Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube -- Network-on-Chip and Secure Computing Architectures -- CASCADE: Congestion Aware Switchable Cycle Adaptive Detection Router -- An Alternating Transmission Scheme for Detection Routing based Network-on-Chips -- Exzess: Hardware-based RAM Encryption against Physical Memory Disclosure -- Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSA -- Cache Architectures and Protocols Adaptive Cache Structures -- Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence -- Mapping of Applications on Heterogeneous -- Architectures and Real-Time Tasks on Multiprocessors Generic algorithmic scheme for 2D stencil applications on heterogeneous hybrid machines -- GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing -- Task Variants with Different Scratchpad Memory Consumption in Multi-Task Environments -- Feedback-Based Admission Control for Hard Real-Time Task Allocation under Dynamic Workload on Many-core Systems -- All About Time: Timing, Tracing, and Performance Modeling Data Age Diminution in the Logical Execution Time Model -- Accurate Sample Time Reconstruction for Sensor Data Synchronization -- DiaSys: On-Chip Trace Analysis for Multi-Processor System-on-Chip -- Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks -- Measurement-Based Probabilistic Timing Analysis for Graphics Processor Units -- Approximate and Energy-Efficient Computing -- Reducing Energy Consumption of Data Transfers using Runtime Data Type Conversion -- Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector -- Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling -- Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting -- Allocation: From Memories to FPGA Hardware Modules Reducing NoC and Memory Contention for Manycores -- An Efficient Data Structure for Dynamic Two-Dimensional Reconfiguration -- Organic Computing Systems Runtime Clustering of Similarly Behaving Agents in Open Organic Computing Systems -- Comparison of Dependency Measures for the Detection of Mutual Influences in Organic Computing Systems -- Augmenting the Algorithmic Structure of XCS by Means of Interpolation -- Reliability Aspects in NoCs, Caches, and GPUs Estimation of End-to-end Packet Error Rates for NoC Multicasts -- Protecting Code Regions on Asymmetrically Reliable Caches -- A New Simulation-based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs. 330 $aThis book constitutes the proceedings of the 29th International Conference on Architecture of Computing Systems, ARCS 2016, held in Nuremberg, Germany, in April 2016. The 29 full papers presented in this volume were carefully reviewed and selected from 87 submissions. They were organized in topical sections named: configurable and in-memory accelerators; network-on-chip and secure computing architectures; cache architectures and protocols; mapping of applications on heterogeneous architectures and real-time tasks on multiprocessors; all about time: timing, tracing, and performance modeling; approximate and energy-efficient computing; allocation: from memories to FPGA hardware modules; organic computing systems; and reliability aspects in NoCs, caches, and GPUs. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v9637 606 $aComputer networks 606 $aComputer systems 606 $aAlgorithms 606 $aSoftware engineering 606 $aApplication software 606 $aComputer science 606 $aComputer Communication Networks 606 $aComputer System Implementation 606 $aAlgorithms 606 $aSoftware Engineering 606 $aComputer and Information Systems Applications 606 $aTheory of Computation 615 0$aComputer networks. 615 0$aComputer systems. 615 0$aAlgorithms. 615 0$aSoftware engineering. 615 0$aApplication software. 615 0$aComputer science. 615 14$aComputer Communication Networks. 615 24$aComputer System Implementation. 615 24$aAlgorithms. 615 24$aSoftware Engineering. 615 24$aComputer and Information Systems Applications. 615 24$aTheory of Computation. 676 $a004.22 702 $aHannig$b Frank$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aCardoso$b João M.P$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aPionteck$b Thilo$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aFey$b Dietmar$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aSchröder-Preikschat$b Wolfgang$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aTeich$b Jürgen$4edt$4http://id.loc.gov/vocabulary/relators/edt 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910483949703321 996 $aArchitecture of Computing Systems -- ARCS 2016$92589708 997 $aUNINA