LEADER 03439oam 2200505 450 001 9910483638003321 005 20220531060254.0 010 $a3-030-54828-7 024 7 $a10.1007/978-3-030-54828-5 035 $a(CKB)4100000011508779 035 $a(DE-He213)978-3-030-54828-5 035 $a(MiAaPQ)EBC6381355 035 $a(PPN)258307293 035 $a(EXLCZ)994100000011508779 100 $a20210416d2021 uy 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aEnhanced virtual prototyping $efeaturing RISC-V case studies /$fVladimir Herdt, Daniel Grosse, Rolf Drechsler 210 1$aCham, Switzerland :$cSpringer,$d[2021] 210 4$d©2021 215 $a1 online resource (XXI, 247 p. 90 illus., 75 illus. in color.) 311 $a3-030-54827-9 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- Preliminaries -- An Open-Source RISC-V Evaluation Platform -- Formal Verification of SystemC-based Designs using Symbolic Simulation -- Coverage-guided Testing for Scalable Virtual Prototype Verification -- Verification of Embedded Software Binaries using Virtual Prototypes -- Validation of Firmware-Based Power Management using Virtual Prototypes -- Register-Transfer Level Correspondence Analysis -- Conclusion -- Index. 330 $aThis book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects. Provides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow Includes automated formal verification methods and advanced coverage-guided testing techniques, tailored for SystemC-based VPs Describes efficient, coverage-guided test generation methods for VP-based functional and non-functional software (SW) analysis and verification Includes correspondence analyses to utilize information between different abstraction levels in the design flow Uses several VP and SW verification case-studies that target the modern RISC-V ISA. 606 $aComputer engineering 606 $aSoftware prototyping 606 $aElectronic circuits 615 0$aComputer engineering. 615 0$aSoftware prototyping. 615 0$aElectronic circuits. 676 $a005.3 700 $aHerdt$b Vladimir$0871290 702 $aDrechsler$b Rolf 702 $aGrosse$b Daniel 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bUtOrBLW 906 $aBOOK 912 $a9910483638003321 996 $aEnhanced virtual prototyping$92851534 997 $aUNINA