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001 9910483227103321
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010   $a981-334-642-6
024 7 $a10.1007/978-981-33-4642-0
035   $a(CKB)4100000011704492
035   $a(DE-He213)978-981-33-4642-0
035   $a(MiAaPQ)EBC6452036
035   $a(PPN)253252091
035   $a(EXLCZ)994100000011704492
100   $a20210319d2021      uy             0
101 0 $aeng
135   $aurnn|008mamaa
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aASIC design and synthesis $eRTL design using Verilog /$fVaibbhav Taraate
205   $a1st ed. 2021.
210  1$aSingapore :$cSpringer,$d[2021]
210  4$dİ2021
215   $a1 online resource (XXI, 330 p. 311 illus., 184 illus. in color.) 
311   $a981-334-641-8 
327   $aChapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
330   $aThis book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
606   $aApplication-specific integrated circuits$xDesign
606   $aVerilog (Computer hardware description language)
615  0$aApplication-specific integrated circuits$xDesign.
615  0$aVerilog (Computer hardware description language)
676   $a621.395
700   $aTaraate$b Vaibbhav$0788080
801  0$bMiAaPQ
801  1$bMiAaPQ
801  2$bMiAaPQ
906   $aBOOK
912   $a9910483227103321
996   $aASIC design and synthesis$92849475
997   $aUNINA