LEADER 06729nam 2200589 450 001 9910467588503321 005 20200520144314.0 010 $a1-119-31397-X 010 $a1-119-31399-6 024 7 $a10.1002/9781119313991 035 $a(CKB)4330000000010179 035 $a(MiAaPQ)EBC5720829 035 $a(CaSebORM)9781119314134 035 $a(Au-PeEL)EBL5720829 035 $a(OCoLC)1089612468 035 $a(CaBNVSL)mat08726249 035 $a(IDAMS)0b0000648935c166 035 $a(IEEE)8726249 035 $a(EXLCZ)994330000000010179 100 $a20190614d2019 uy 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 00$aAdvances in embedded and fan-out wafer level packaging technologies /$fedited by Beth Keser and Steffen Kro?hnert 205 $a1st edition 210 1$aHoboken, New Jersey, USA :$cJohn Wiley & Sons, Inc.,$d2019. 210 2$a[Piscataqay, New Jersey] :$cIEEE Xplore,$d[2019] 215 $a1 online resource (xxvii, 548 pages) $cillustrations 311 $a1-119-31413-5 320 $aIncludes bibliographical references and index. 327 $aPreface xvii -- List of Contributors xxiii -- Acknowledgments xxvii -- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang -- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman -- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert -- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon -- 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim -- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan -- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger -- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu -- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann -- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle -- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata -- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf -- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon -- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe -- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen -- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner -- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi. 327 $a18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung -- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro -- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee -- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Povazay -- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon -- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama -- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir -- References 515 -- Index 521. 330 $aExamines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges Embedded and fan-out wafer level packaging "FO-WLP" technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons. Filled with contributions from some of the field's leading experts,??Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. This valuable text: . Discusses specific company standards and their development results. Relates its content to practice as well as to contemporary and future challenges in electronics system integration and packaging Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research. 606 $aIntegrated circuits 606 $aIntegrated circuits$xWafer-scale integration 606 $aChip scale packaging 608 $aElectronic books. 615 0$aIntegrated circuits. 615 0$aIntegrated circuits$xWafer-scale integration. 615 0$aChip scale packaging. 676 $a621.38173 702 $aKeser$b Beth$f1971- 702 $aKroehnert$b Steffen$f1970- 801 0$bCaBNVSL 801 1$bCaBNVSL 801 2$bCaBNVSL 906 $aBOOK 912 $a9910467588503321 996 $aAdvances in embedded and fan-out wafer level packaging technologies$92260804 997 $aUNINA