LEADER 02837nam 22006252 450 001 9910462717003321 005 20151005020621.0 010 $a1-139-89228-2 010 $a1-107-42435-6 010 $a1-107-42241-8 010 $a1-107-41933-6 010 $a1-107-41667-1 010 $a1-107-42053-9 010 $a1-139-34441-2 035 $a(CKB)2670000000433764 035 $a(EBL)1394552 035 $a(OCoLC)863821797 035 $a(SSID)ssj0000999472 035 $a(PQKBManifestationID)12346496 035 $a(PQKBTitleCode)TC0000999472 035 $a(PQKBWorkID)10933920 035 $a(PQKB)10948922 035 $a(UkCbUP)CR9781139344418 035 $a(MiAaPQ)EBC1394552 035 $a(Au-PeEL)EBL1394552 035 $a(CaPaEBR)ebr10795369 035 $a(OCoLC)862126128 035 $a(EXLCZ)992670000000433764 100 $a20120320d2013|||| uy| 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 14$aThe Company States Keep $eInternational economic organizations and investor perceptions /$fJulia Gray, University of Pennsylvania$b[electronic resource] 210 1$aCambridge :$cCambridge University Press,$d2013. 215 $a1 online resource (xiv, 234 pages) $cdigital, PDF file(s) 300 $aTitle from publisher's bibliographic system (viewed on 05 Oct 2015). 311 $a1-107-56682-7 311 $a1-107-03088-9 320 $aIncludes bibliographical references and index. 327 $tIntroduction: the company you keep --$tInternational institutions and sovereign risk --$tThe company you keep in comparative perspective --$tThe effects of Good Company --$tWhen emerging markets join up with Bad Company --$tHow risk for core members changes on IO expansion --$tConclusion. 330 $aThis book argues that investor risk in emerging markets hinges on the company a country keeps. When a country signs on to an economic agreement with states that are widely known to be stable, it looks less risky. Conversely, when a country joins a group with more unstable members, it looks more risky. Investors use the company a country keeps as a heuristic in evaluating that country's willingness to honor its sovereign debt obligations. This has important implications for the study of international cooperation as well as of sovereign risk and credibility at the domestic level. 606 $aDebts, Public$zDeveloping countries 606 $aInternational agencies 615 0$aDebts, Public 615 0$aInternational agencies. 676 $a336.3/435091724 700 $aGray$b Julia$f1974-$01026707 801 0$bUkCbUP 801 1$bUkCbUP 906 $aBOOK 912 $a9910462717003321 996 $aThe Company States Keep$92441776 997 $aUNINA LEADER 03590oam 2200421zu 450 001 996218410303316 005 20210806235758.0 010 $a1-5090-9982-4 035 $a(CKB)1000000000278028 035 $a(SSID)ssj0000396086 035 $a(PQKBManifestationID)12111761 035 $a(PQKBTitleCode)TC0000396086 035 $a(PQKBWorkID)10464869 035 $a(PQKB)10259984 035 $a(NjHacI)991000000000278028 035 $a(EXLCZ)991000000000278028 100 $a20160829d2005 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 00$a2005 international conference on reconfigurable computing and FPGAS 210 31$a[Place of publication not identified]$cIEEE Computer Society$d2005 215 $a1 online resource (183 pages) $cillustrations 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a0-7695-2456-7 327 $aReal-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling, -- An image comparison circuit design," -- FPGA-based customizable systolic architecture for image processing applications," -- An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method," -- Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform," -- A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays," -- Rapid prototyping of a self-timed ALU with FPGAs," -- FPGA implementation of a synchronous and self-timed neuroprocessor," -- On the design of two-level reconfigurable architectures," -- A secure self-reconfiguring architecture based on open-source hardware," -- Platform for intrinsic evolution of analogue neural networks," -- High quality uniform random number generation for massively parallel simulations in FPGA," -- VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks," -- Quartz: a framework for correct and efficient reconfigurable design," -- Design space exploration of coarse-grain reconfigurable DSPs," -- Optimizing register binding in FPGAs using simulated annealing," -- An FPGA-based parallel sorting architecture for the Burrows Wheeler transform," -- Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices," -- Applied VHDL training methodology, EDA framework and hardware implementation platform," -- FPGA implementation of DSVPWM modulator," -- A novel FPGA implementation of a welding control using a new bus architecture," -- On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004," -- Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3," -- VHDL core for 1024-point radix-4 FFT computation," -- Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation," -- FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)," -- An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences," -- Hardware/software implementation of a discrete cosine transform algorithm using SystemC. 606 $aAdaptive computing systems$vCongresses 615 0$aAdaptive computing systems 676 $a004 702 $aFeregrino$b Claudia 702 $aCumplido$b Rene? 801 0$bPQKB 906 $aPROCEEDING 912 $a996218410303316 996 $a2005 international conference on reconfigurable computing and FPGAS$92364582 997 $aUNISA