LEADER 01122nam2-2200373---450- 001 990001309770203316 005 20070831125637.0 035 $a000130977 035 $aUSA01000130977 035 $a(ALEPH)000130977USA01 035 $a000130977 100 $a20031219d1969----km-y0itay0103----ba 101 0 $afre 102 $aFR 105 $aa|||||||001yy 200 1 $a<> : Jacques-Rene Hebert$fintroduction par Albert Soboul 210 $aParis$cEDHIS$d1969 215 $a1 v.(paginazione varia)$cill.$d18 cm 410 0$12001 454 1$12001 461 1$1001000130964$12001$aLe Père Duchesne: 1790-1794 700 1$aHEBERT,$bJacques-Rene$0557494 701 1$aSOBOUL,$bAlbert$0134927 801 0$aIT$bsalbc$gISBD 912 $a990001309770203316 951 $aX.2.A. 51/8(III D 485/8)$b13195 L.M.$cIII D 959 $aBK 969 $aUMA 979 $aSIAV6$b10$c20031219$lUSA01$h1000 979 $aPATRY$b90$c20040406$lUSA01$h1733 979 $aCOPAT3$b90$c20050401$lUSA01$h1240 979 $aCOPAT1$b90$c20070831$lUSA01$h1256 996 $aJacques-Rene Hebert$9929011 997 $aUNISA LEADER 02566nam 2200613Ia 450 001 9910459735803321 005 20200520144314.0 010 $a1-282-82009-5 010 $a9786612820090 010 $a0-7391-4441-3 035 $a(CKB)2670000000066404 035 $a(EBL)634251 035 $a(OCoLC)669516057 035 $a(SSID)ssj0000418623 035 $a(PQKBManifestationID)12156688 035 $a(PQKBTitleCode)TC0000418623 035 $a(PQKBWorkID)10377435 035 $a(PQKB)10722877 035 $a(MiAaPQ)EBC634251 035 $a(Au-PeEL)EBL634251 035 $a(CaPaEBR)ebr10421419 035 $a(CaONFJC)MIL282009 035 $a(EXLCZ)992670000000066404 100 $a20100701d2010 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aGetting a cut$b[electronic resource] $ea contextual understanding of commission systems /$fRichard Seltzer and Holona LeAnne Ochs 210 $aLanham, MD $cLexington Books$dc2010 215 $a1 online resource (165 p.) 300 $aDescription based upon print version of record. 311 $a0-7391-4439-1 320 $aIncludes bibliographical references and index. 327 $aContents; Preface; Introduction; Chapter 01. Travel; Chapter 02. Financial Services; Chapter 03. Realty; Chapter 04. Agents; Chapter 05. Direct Marketing; Chapter 06. Clothes, Jewelry, and Cosmetics; Chapter 07. Electronics; Chapter 08. Auto Parts, Sales, and Service; Chapter 09. Miscellaneous; Conclusions; References; Index; About the Authors 330 $aGetting a Cut provides a perspective on nonstandard compensation that demonstrates the process by which commissions impact the experiences of workers. Understanding this under-researched perspective reveals a great deal about the process by which the interaction of structure, culture, and craft that define management practices shape the experiences of the sales force and have the potential to enhance organizational performance. 606 $aWage payment systems 606 $aBonus system 606 $aCommission merchants 608 $aElectronic books. 615 0$aWage payment systems. 615 0$aBonus system. 615 0$aCommission merchants. 676 $a331.2/164 700 $aSeltzer$b Richard$cPh. D.$0889602 701 $aOchs$b Holona LeAnne$0950095 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910459735803321 996 $aGetting a cut$92267982 997 $aUNINA LEADER 01692nam 2200541 450 001 9910467035403321 005 20210907152233.0 010 $a1-60258-379-X 010 $a1-60258-378-1 035 $a(CKB)3780000000105322 035 $a(MiAaPQ)EBC4863646 035 $a(OCoLC)868219477 035 $a(MdBmJHUP)muse28342 035 $a(Au-PeEL)EBL4863646 035 $a(CaPaEBR)ebr11387554 035 $a(OCoLC)988176396 035 $a(EXLCZ)993780000000105322 100 $a20170616h20122012 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $2rdacontent 182 $2rdamedia 183 $2rdacarrier 200 10$aShows about nothing $enihilism in popular culture /$fThomas S. Hibbs 205 $a2nd rev. and expanded ed. 210 1$aWaco, Texas :$cBaylor University Press,$d2012. 210 4$d©2012 215 $a1 online resource (276 pages) $cillustrations 311 $a1-60258-378-1 320 $aIncludes bibliographical references at the end of each chapters and index. 606 $aNihilism (Philosophy) in motion pictures 606 $aNihilism (Philosophy) on television 606 $aEvil in motion pictures 606 $aCulture in motion pictures 608 $aElectronic books. 615 0$aNihilism (Philosophy) in motion pictures. 615 0$aNihilism (Philosophy) on television. 615 0$aEvil in motion pictures. 615 0$aCulture in motion pictures. 676 $a791.43684 700 $aHibbs$b Thomas S.$0772757 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910467035403321 996 $aShows about nothing$92479817 997 $aUNINA LEADER 05768nam 2200745Ia 450 001 9910141240503321 005 20200520144314.0 010 $a1-283-28288-7 010 $a9786613282880 010 $a1-118-14653-0 010 $a1-118-14652-2 010 $a1-118-14650-6 035 $a(CKB)2670000000128082 035 $a(EBL)817361 035 $a(OCoLC)757486963 035 $a(SSID)ssj0000554671 035 $a(PQKBManifestationID)11308402 035 $a(PQKBTitleCode)TC0000554671 035 $a(PQKBWorkID)10516823 035 $a(PQKB)10946358 035 $a(MiAaPQ)EBC817361 035 $a(Au-PeEL)EBL817361 035 $a(CaPaEBR)ebr10560671 035 $a(CaONFJC)MIL328288 035 $a(PPN)179237667 035 $a(EXLCZ)992670000000128082 100 $a20110527d2011 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aEmbedded SOPC design with NIOS II processor and VHDL examples$b[electronic resource] /$fPong P. Chu 210 $aHoboken, N.J. $cWiley$dc2011 215 $a1 online resource (738 p.) 300 $aDescription based upon print version of record. 311 $a1-118-00888-X 320 $aIncludes bibliographical references and index. 327 $aEmbedded SOPC Design with Nios II Processor and VHDL Examples; CONTENTS; Preface; Acknowledgments; 1 Overview of Embedded System; 1.1 Introduction; 1.1.1 Definition of an embedded system; 1.1.2 Example systems; 1.2 System design requirements; 1.3 Embedded SoPC systems; 1.3.1 Basic development flow; 1.4 Book organization; 1.5 Bibliographic notes; PART I BASIC DIGITAL CIRCUITS DEVELOPMENT; 2 Gate-level Combinational Circuit; 2.1 Overview of VHDL; 2.2 General description; 2.2.1 Basic lexical rules; 2.2.2 Library and package; 2.2.3 Entity declaration; 2.2.4 Data type and operators 327 $a2.2.5 Architecture body2.2.6 Code of a 2-bit comparator; 2.3 Structural description; 2.4 Testbench; 2.5 Bibliographic notes; 2.6 Suggested experiments; 2.6.1 Code for gate-level greater-than circuit; 2.6.2 Code for gate-level binary decoder; 3 Overview of FPGA and EDA Software; 3.1 FPGA; 3.1.1 Overview of a general FPGA device; 3.1.2 Overview of the Altera Cyclone II devices; 3.2 Overview of the Altera DE1 and DE2 boards; 3.3 Development flow; 3.4 Overview of Quartus II; 3.5 Short tutorial of Quartus II; 3.5.1 Create the design project; 3.5.2 Create a testbench and perform the RTL simulation 327 $a3.5.3 Compile the project3.5.4 Perform timing analysis; 3.5.5 Program the FPGA device; 3.6 Short tutorial on the ModelSim HDL simulator; 3.7 Bibliographic notes; 3.8 Suggested experiments; 3.8.1 Gate-level greater-than circuit; 3.8.2 Gate-level binary decoder; 4 RT-level Combinational Circuit; 4.1 RT-level components; 4.1.1 Relational operators; 4.1.2 Arithmetic operators; 4.1.3 Other synthesis-related VHDL constructs; 4.1.4 Summary; 4.2 Routing circuit with concurrent assignment statements; 4.2.1 Conditional signal assignment statement; 4.2.2 Selected signal assignment statement 327 $a4.3 Modeling with a process4.3.1 Process; 4.3.2 Sequential signal assignment statement; 4.4 Routing circuit with if and case statements; 4.4.1 If statement; 4.4.2 Case statement; 4.4.3 Comparison to concurrent statements; 4.4.4 Unintended memory; 4.5 Constants and generics; 4.5.1 Constants; 4.5.2 Generics; 4.6 Design examples; 4.6.1 Hexadecimal digit to seven-segment LED decoder; 4.6.2 Sign-magnitude adder; 4.6.3 Barrel shifter; 4.6.4 Simplified floating-point adder; 4.7 Bibliographic notes; 4.8 Suggested experiments; 4.8.1 Multi-function barrel shifter; 4.8.2 Dual-priority encoder 327 $a4.8.3 BCD incrementor4.8.4 Floating-point greater-than circuit; 4.8.5 Floating-point and signed integer conversion circuit; 4.8.6 Enhanced floating-point adder; 5 Regular Sequential Circuit; 5.1 Introduction; 5.1.1 D FF and register; 5.1.2 Synchronous system; 5.1.3 Code development; 5.2 HDL code of the basic storage elements; 5.2.1 D FF; 5.2.2 Register; 5.2.3 Register file; 5.2.4 SRAM; 5.3 Simple design examples; 5.3.1 Shift register; 5.3.2 Binary counter and variant; 5.4 Testbench for sequential circuits; 5.5 Timing analysis; 5.5.1 Timing parameters; 5.5.2 Timing considerations in Quartus II 327 $a5.6 Case study 330 $aThe book is divided into four major parts. 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