LEADER 04966nam 2200685 a 450 001 9910458595103321 005 20200520144314.0 010 $a1-280-96683-1 010 $a9786610966837 010 $a0-08-047356-3 035 $a(CKB)1000000000364108 035 $a(EBL)288756 035 $a(OCoLC)469401810 035 $a(SSID)ssj0000076804 035 $a(PQKBManifestationID)11115919 035 $a(PQKBTitleCode)TC0000076804 035 $a(PQKBWorkID)10031849 035 $a(PQKB)11393075 035 $a(MiAaPQ)EBC288756 035 $a(CaSebORM)9780123705211 035 $a(Au-PeEL)EBL288756 035 $a(CaPaEBR)ebr10169631 035 $a(CaONFJC)MIL96683 035 $a(EXLCZ)991000000000364108 100 $a20060605d2006 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aNetworks on chips$b[electronic resource] $etechnology and tools /$fLuca Benini and Giovanni De Micheli 205 $a1st edition 210 $aAmsterdam ;$aBoston $cElsevier Morgan Kaufmann Publishers$dc2006 215 $a1 online resource (408 p.) 225 1 $aThe Morgan Kaufmann series in systems on silicon 300 $aDescription based upon print version of record. 311 $a1-4933-0082-2 311 $a0-12-370521-5 320 $aIncludes bibliographical references and index. 327 $aFront Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling 327 $a3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs 327 $a5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study 327 $a6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index 330 $aThe design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a compl 410 0$aMorgan Kaufmann series in systems on silicon. 606 $aSystems on a chip 606 $aComputer networks$xEquipment and supplies 608 $aElectronic books. 615 0$aSystems on a chip. 615 0$aComputer networks$xEquipment and supplies. 676 $a621.3815 700 $aBenini$b Luca$f1967-$0871375 701 $aDe Micheli$b Giovanni$0770515 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910458595103321 996 $aNetworks on chips$92084710 997 $aUNINA