LEADER 05470nam 2200673Ia 450 001 9910458468403321 005 20200520144314.0 010 $a1-280-62622-4 010 $a9786610626229 010 $a0-08-051250-X 035 $a(CKB)1000000000364704 035 $a(EBL)232128 035 $a(OCoLC)171114501 035 $a(SSID)ssj0000209410 035 $a(PQKBManifestationID)12021399 035 $a(PQKBTitleCode)TC0000209410 035 $a(PQKBWorkID)10286244 035 $a(PQKB)11216138 035 $a(MiAaPQ)EBC232128 035 $a(Au-PeEL)EBL232128 035 $a(CaPaEBR)ebr10127983 035 $a(CaONFJC)MIL62622 035 $a(OCoLC)936897711 035 $a(EXLCZ)991000000000364704 100 $a20050617d2005 fy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 00$aIssues and practices$b[electronic resource] /$fedited by Patrick Crowley ... [et al.] 210 $aSan Francisco $cMorgan Kaufmann$d2005 215 $a1 online resource (335 p.) 225 0 $aNetwork processor design ;$v3 300 $aDescription based upon print version of record. 311 $a0-12-088476-3 320 $aIncludes bibliographical references and index. 327 $aFront Cover; Network Processor Design Issues and Practices; Copyright Page; About the Editors; Contents; Preface; Chapter 1. Network Processors: New Horizons; 1.1 Architecture; 1.2 Tools and Techniques; 1.3 Applications; 1.4 Conclusions; References; Chapter 2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches; 2.1 Instruction Delivery in NP Data Processors; 2.2 Segmented Instruction Cache; 2.3 Experimental Evaluation; 2.4 Related Work; 2.5 Conclusions and Future Work; References; Chapter 3. Efficient Packet Classification with Digest Caches 327 $a3.1 Related Work3.2 Our Approach; 3.3 Evaluation; 3.4 Hardware Overhead; 3.5 Conclusions; Acknowledgments; References; Chapter 4. Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express; 4.1 Interface Fundamentals and Comparison; 4.2 Modeling the Interfaces; 4.3 Architecture Evaluation; 4.4 Conclusions; Acknowledgments; References; Chapter 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet; 5.1 Requirements on TCP Offload Solution; 5.2 Architecture of TOE Solution; 5.3 Performance Analysis; 5.4 Conclusions; Acknowledgments; References 327 $aChapter 6. A Hardware Platform for Network Intrusion Detection and Prevention6.1 Design Rationales and Principles; 6.2 Prototype NNIDS on a Network Interface; 6.3 Evaluation and Results; 6.4 Conclusions; References; Chapter 7. Packet Processing on a SIMD Stream Processor; 7.1 Background: Stream Programs and Architectures; 7.2 AES Encryption; 7.3 IPv4 Forwarding; 7.4 Related Work; 7.5 Conclusions and Future Work; Acknowledgments; References; Chapter 8. A Programming Environment for Packet-Processing Systems: Design Considerations; 8.1 Problem Domain 327 $a8.2 Shangri-La. A Programming Environment for Packet-Processing Systems 1508.3 Design Details and Challenges; 8.4 Conclusions; References; Chapter 9. RNOS-A Middleware Platform for Low-Cost Packet-Processing Devices; 9.1 Scenario; 9.2 Analysis Model of RNOS; 9.3 Implementation Model of RNOS; 9.4 Measurements and Comparison; 9.5 Conclusions and Outlook; Acknowledgments; References; Chapter 10. On the Feasibility of Using Network Processors for DNA Queries; 10.1 Architecture; 10.2 Implementation Details; 10.3 Results; 10.4 Related Work; 10.5 Conclusions; Acknowledgments; References 327 $aChapter 11. Pipeline Task Scheduling on Network Processors11.1 The Pipeline Task Assignment Problem; 11.2 The Greedypipe Algorithm; 11.3 Pipeline Design with Greedypipe; 11.4 A Network Processor Problem; 11.5 Conclusions; Acknowledgments; References; Chapter 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs; 12.1 Related Work; 12.2 Modeling Packet-Processing Systems; 12.3 Scheduling; 12.4 Mapping the Application to the System; 12.5 Estimating the Resource Consumption; 12.6 A Design Space Exploration Example; 12.7 Conclusions 327 $aAcknowledgments 330 $aThe past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors. Through chapters on hardware, software, performance and modeling, Volume 3 illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.Like Volume 2 of the series, Volume 3 f 410 4$aThe Morgan Kaufmann Series in Computer Architecture and Design 606 $aNetwork processors$xDesign 606 $aApplication-specific integrated circuits$xDesign 608 $aElectronic books. 615 0$aNetwork processors$xDesign. 615 0$aApplication-specific integrated circuits$xDesign. 676 $a621.395 701 $aCrowley$b Patrick$0874890 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910458468403321 996 $aIssues and practices$92227446 997 $aUNINA