LEADER 03465nam 2200709 a 450 001 9910457690303321 005 20200520144314.0 010 $a1-61811-039-X 024 7 $a10.1515/9781618110398 035 $a(CKB)2550000000063136 035 $a(EBL)3110391 035 $a(SSID)ssj0000565427 035 $a(PQKBManifestationID)12243971 035 $a(PQKBTitleCode)TC0000565427 035 $a(PQKBWorkID)10528157 035 $a(PQKB)10780003 035 $a(MiAaPQ)EBC3110391 035 $a(DE-B1597)541032 035 $a(OCoLC)767644715 035 $a(DE-B1597)9781618110398 035 $a(Au-PeEL)EBL3110391 035 $a(CaPaEBR)ebr10509016 035 $a(CaONFJC)MIL574363 035 $a(EXLCZ)992550000000063136 100 $a20080324d2008 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aTime and life cycle in Talmud and Midrash$b[electronic resource] $esocio-anthropological perspectives /$fNissan Rubin 210 $aBoston $cAcademic Studies Press$d2008 215 $a1 online resource (236 p.) 225 1 $aJudaism and Jewish life 300 $aDescription based upon print version of record. 311 $a1-934843-07-5 320 $aIncludes bibliographical references (p. 193-[209]) and indexes. 327 $aThe sociology and anthropology of Talmudic texts -- The clothing of the primordial Adam as a symbol of apocalyptic time in the Midrashic sources -- Brit milah: a study of change in custom -- Coping with the value of the Pidyon ha?ben payment in rabbinic literature: an example of a social change process -- Birth and marriage rituals: women's status in a critical reading of the texts -- The sages' conception of the body and soul -- From corpse to corpus: the body as a text in Talmudic literature -- Birkat avelim--the blessing of mourners: ritual aspects of social change. 330 $aFocusing on the concepts of time and the life cycle, this collection of articles examines Jewish life in the Talmudic period through the lens of Jewish law and custom of the time. The essays are the work of Nissan Rubin (one of them written in collaboration with Admiel Kosman) and come together to present the cultural perspective of the sages and scholars who produced the stepping-stones of Jewish life and custom. By using a structural approach, Rubin is able to identify processes of long-term change in a society that remains largely traditional and stable. Symbolic analysis supplies an additional dimension to these studies, enabling the reader to experience the cultural subtexts. 410 0$aJudaism and Jewish life. 606 $aJudaism$xCustoms and practices 606 $aLife cycle, Human$xReligious aspects$xJudaism 606 $aRabbinical literature$xHistory and criticism 606 $aMidrash 606 $aSociology 606 $aAnthropology 608 $aElectronic books. 615 0$aJudaism$xCustoms and practices. 615 0$aLife cycle, Human$xReligious aspects$xJudaism. 615 0$aRabbinical literature$xHistory and criticism. 615 0$aMidrash. 615 0$aSociology. 615 0$aAnthropology. 676 $a296.1/206 700 $aRubin$b Nissan$01044030 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910457690303321 996 $aTime and life cycle in Talmud and Midrash$92474855 997 $aUNINA LEADER 08320nam 22008895 450 001 9910485025903321 005 20251226195432.0 010 $a3-540-95948-3 024 7 $a10.1007/978-3-540-95948-9 035 $a(CKB)1000000000575766 035 $a(SSID)ssj0000318341 035 $a(PQKBManifestationID)11226186 035 $a(PQKBTitleCode)TC0000318341 035 $a(PQKBWorkID)10307543 035 $a(PQKB)11444973 035 $a(DE-He213)978-3-540-95948-9 035 $a(MiAaPQ)EBC3063922 035 $a(PPN)132870762 035 $a(EXLCZ)991000000000575766 100 $a20100301d2009 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt 182 $cc 183 $acr 200 10$aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation $e18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers /$fedited by Lars Svensson, José Monteiro 205 $a1st ed. 2009. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2009. 215 $a1 online resource (XIII, 462 p.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5349 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a3-540-95947-5 320 $aIncludes bibliographical references and index. 327 $aSession 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope. 330 $aThis book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v5349 606 $aLogic design 606 $aMicroprocessors 606 $aComputer architecture 606 $aElectronic digital computers$xEvaluation 606 $aComputer arithmetic and logic units 606 $aComputer storage devices 606 $aMemory management (Computer science) 606 $aElectronic circuits 606 $aLogic Design 606 $aProcessor Architectures 606 $aSystem Performance and Evaluation 606 $aArithmetic and Logic Structures 606 $aComputer Memory Structure 606 $aElectronic Circuits and Systems 615 0$aLogic design. 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aElectronic digital computers$xEvaluation. 615 0$aComputer arithmetic and logic units. 615 0$aComputer storage devices. 615 0$aMemory management (Computer science) 615 0$aElectronic circuits. 615 14$aLogic Design. 615 24$aProcessor Architectures. 615 24$aSystem Performance and Evaluation. 615 24$aArithmetic and Logic Structures. 615 24$aComputer Memory Structure. 615 24$aElectronic Circuits and Systems. 676 $a620/.004202825536 686 $aDAT 190f$2stub 686 $aELT 272f$2stub 686 $aSS 4800$2rvk 701 $aSvensson$b Lars$f1960-$01750257 701 $aMonteiro$b Jose?$f1966-$00 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910485025903321 996 $aIntegrated Circuit and System Design. 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