LEADER 01150nam--2200397---450- 001 990002851470203316 005 20070109085401.0 010 $a88-15-00562-5 035 $a000285147 035 $aUSA01000285147 035 $a(ALEPH)000285147USA01 035 $a000285147 100 $a20070109d1984----km-y0itay50------ba 101 $aita 102 $aIT 105 $a||||||||001yy 200 1 $aRodolfo 2. d'Absburgo$el'enigma di un imperatore$fRobert J. W. Evans 210 $aBologna$c<> mulino$d1984 215 $a445 p.$cc. geogr.$d22 cm 225 2 $aBiblioteca storica 300 $aTrad. di Alfonso Prandi 300 $a[Titolo originale] Rudolf 2. and his world 410 0$12001$aBiblioteca storica 454 1$12001 461 1$1001-------$12001 600 0 $aRodolfo Imperatore 2 676 $a943.034 700 1$aEVANS,$bRobert J. W.$0120022 801 0$aIT$bsalbc$gISBD 912 $a990002851470203316 951 $a943.034 EVA$b19 DITESI (armadio 1 I n.45) 959 $aBK 969 $aDITESI 979 $aDITESI$b10$c20070109$lUSA01$h0854 996 $aRodolfo 2. d'Absburgo$9992792 997 $aUNISA LEADER 05378nam 2200673Ia 450 001 9910456662303321 005 20200520144314.0 010 $a1-282-75584-6 010 $a9786612755842 010 $a1-85617-964-8 035 $a(CKB)2530000000000382 035 $a(EBL)535305 035 $a(OCoLC)635293745 035 $a(SSID)ssj0000435323 035 $a(PQKBManifestationID)11276039 035 $a(PQKBTitleCode)TC0000435323 035 $a(PQKBWorkID)10420701 035 $a(PQKB)11673322 035 $a(MiAaPQ)EBC535305 035 $a(CaSebORM)9781856179638 035 $a(PPN)17060456X 035 $a(Au-PeEL)EBL535305 035 $a(CaPaEBR)ebr10379020 035 $a(CaONFJC)MIL275584 035 $a(EXLCZ)992530000000000382 100 $a20091013d2010 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 14$aThe definitive guide to the ARM Cortex-M3$b[electronic resource] /$fJoseph Yiu 205 $a2nd ed. 210 $aAmsterdam ;$aBoston $cNewnes$dc2010 215 $a1 online resource (481 p.) 300 $aDescription based upon print version of record. 311 $a1-85617-963-X 320 $aIncludes bibliographical references and index. 327 $aFront Cover; Half Title Page; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1. Introduction; 1.1 What Is the ARM Cortex-M3 Processor?; 1.2 Background of ARM and ARM Architecture; 1.2.1 A Brief History; 1.2.2 Architecture Versions; 1.2.3 Processor Naming; 1.3 Instruction Set Development; 1.4 The Thumb-2 Technology and Instruction Set Architecture; 1.5 Cortex-M3 Processor Applications; 1.6 Organization of This Book; 1.7 Further Reading; Chapter 2. Overview of the Cortex-M3 327 $a2.1 Fundamentals2.2 Registers; 2.2.1 R0-R12: General-Purpose Registers; 2.2.2 R13: Stack Pointers; 2.2.3 R14: The Link Register; 2.2.4 R15: The Program Counter; 2.2.5 Special Registers; 2.3 Operation Modes; 2.4 The Built-In Nested Vectored Interrupt Controller; 2.4.1 Nested Interrupt Support; 2.4.2 Vectored Interrupt Support; 2.4.3 Dynamic Priority Changes Support; 2.4.4 Reduction of Interrupt Latency; 2.4.5 Interrupt Masking; 2.5 The Memory Map; 2.6 The Bus Interface; 2.7 The MPU; 2.8 The Instruction Set; 2.9 Interrupts and Exceptions; 2.9.1 Low Power and High Energy Efficiency 327 $a2.10 Debugging Support2.11 Characteristics Summary; 2.11.1 High Performance; 2.11.2 Advanced Interrupt-Handling Features; 2.11.3 Low Power Consumption; 2.11.4 System Features; 2.11.5 Debug Supports; Chapter 3. Cortex-M3 Basics; 3.1 Registers; 3.1.1 General Purpose Registers R0 through R7; 3.1.2 General Purpose Registers R8 through R12; 3.1.3 Stack Pointer R13; 3.1.4 Link Register R14; 3.1.5 Program Counter R15; 3.2 Special Registers; 3.2.1 Program Status Registers; 3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers; 3.2.3 The Control Register; 3.3 Operation Mode; 3.4 Exceptions and Interrupts 327 $a3.5 Vector Tables3.6 Stack Memory Operations; 3.6.1 Basic Operations of the Stack; 3.6.2 Cortex-M3 Stack Implementation; 3.6.3 The Two-Stack Model in the Cortex-M3; 3.7 Reset Sequence; Chapter 4. Instruction Sets; 4.1 Assembly Basics; 4.1.1 Assembler Language: Basic Syntax; 4.1.2 Assembler Language: Use of Suffixes; 4.1.3 Assembler Language: Unified Assembler Language; 4.2 Instruction List; 4.2.1 Unsupported Instructions; 4.3 Instruction Descriptions; 4.3.1 Assembler Language: Moving Data; 4.3.2 LDR and ADR Pseudo-Instructions; 4.3.3 Assembler Language: Processing Data 327 $a4.3.4 Assembler Language: Call and Unconditional Branch4.3.5 Assembler Language: Decisions and Conditional Branches; 4.3.6 Assembler Language: Combined Compare and Conditional Branch; 4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions; 4.3.8 Assembly Language: Saturation Operations; 4.4 Several Useful Instructions in the Cortex-M3; 4.4.1 MSR and MRS; 4.4.2 More on the IF-THEN Instruction Block; 4.4.3 SDIV and UDIV; 4.4.4 REV, REVH, and REVSH; 4.4.5 Reverse Bit; 4.4.6 SXTB, SXTH, UXTB, and UXTH; 4.4.7 Bit Field Clear and Bit Field Insert; 4.4.8 UBFX and SBFX 327 $a4.4.9 LDRD and STRD 330 $aThis user's guide does far more than simply outline the ARM Cortex-M3 CPU features; it explains step-by-step how to program and implement the processor in real-world designs. It teaches readers how to utilize the complete and thumb instruction sets in order to obtain the best functionality, efficiency, and reuseability. The author, an ARM engineer who helped develop the core, provides many examples and diagrams that aid understanding. Quick reference appendices make locating specific details a snap! Whole chapters are dedicated to: Debugging using the new CoreSight technologyMi 606 $aEmbedded computer systems 606 $aMicroprocessors 608 $aElectronic books. 615 0$aEmbedded computer systems. 615 0$aMicroprocessors. 676 $a621.39/16 700 $aYiu$b Joseph$0895135 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910456662303321 996 $aThe definitive guide to the ARM Cortex-M3$92011199 997 $aUNINA