LEADER 04618nam 22007214a 450 001 9910451878903321 005 20200520144314.0 010 $a6611029842 010 $a1-281-02984-X 010 $a9786611029845 010 $a1-60750-261-5 010 $a600-00-0368-4 010 $a1-4356-0867-4 035 $a(CKB)1000000000479707 035 $a(EBL)320319 035 $a(OCoLC)476117136 035 $a(SSID)ssj0000125683 035 $a(PQKBManifestationID)11148142 035 $a(PQKBTitleCode)TC0000125683 035 $a(PQKBWorkID)10026924 035 $a(PQKB)10644291 035 $a(MiAaPQ)EBC320319 035 $a(Au-PeEL)EBL320319 035 $a(CaPaEBR)ebr10196594 035 $a(CaONFJC)MIL102984 035 $a(EXLCZ)991000000000479707 100 $a20070525d2007 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aCommunicating process architectures 2007$b[electronic resource] $eWoTUG-30 : proceedings of the 30th WoTUG Technical Meeting, 8-11 July 2007, University of Surrey, Guildford, United Kingdom /$fedited by Alistair A. McEwan ... [et al.] 210 $aAmsterdam $aFairfax, VA $cIOS Press$d2007 215 $a1 online resource (528 p.) 225 1 $aConcurrent systems engineering series ;$vv. 65 300 $aDescription based upon print version of record. 311 $a1-58603-767-6 327 $aTitle page; Preface; Programme Committee; Additional Reviewers; Contents; Fine-Grain Concurrency; Communicating Process Architecture for Multicores; Lazy Exploration and Checking of CSP Models with CSPsim; The Core Language of Aldwych; JCSProB: Implementing Integrated Formal Specifications in Concurrent Java; Components with Symbolic Transition Systems: A Java Implementation of Rendezvous; Concurrent/Reactive System Design with Honeysuckle; CSP and Real-Time: Reality or Illusion?; Testing and Sampling Parallel Systems; Mobility in JCSP: New Mobile Channel and Mobile Process Models 327 $aC++CSP2: A Many-to-Many Threading Model for Multicore ArchitecturesDesign Principles of the SystemCSP Software Framework; PyCSP - Communicating Sequential Processes for Python; A Process-Oriented Architecture for Complex System Modelling; Concurrency Control and Recovery Management for Open e-Business Transactions; trancell - An Experimental ETC to Cell BE Translator; A Versatile Hardware-Software Platform for In-Situ Monitoring Systems; High Cohesion and Low Coupling: The Office Mapping Factor; A Process Oriented Approach to USB Driver Development 327 $aA Native Transterpreter for the LEGO Mindstorms RCXIntegrating and Extending JCSP; Hardware/Software Synthesis and Verification Using Esterel; Modeling and Analysis of the AMBA Bus Using CSP and B; A Step Towards Refining and Translating B Control Annotations to Handel-C; Towards the Formal Verification of a Java Processor in Event-B; Advanced System Simulation, Emulation and Test (ASSET); Development of a Family of Multi-Core Devices Using Hierarchical Abstraction; Domain Specific Transformations for Hardware Ray Tracing 327 $aA Reconfigurable System-on-Chip Architecture for Pico-Satellite MissionsTransactional CSP Processes; Algebras of Actions in Concurrent Processes; Using occam-pi Primitives with the Cell Broadband Engine; Shared-Memory Multi-Processor Scheduling Algorithms for CCSP; Compiling occam to C with Tock; Author Index 330 $aDeals with Computer Science and models of Concurrency. This title emphasizes on hardware/software co-design and the understanding of concurrency that results from these systems. It includes a range of papers on this topic, from the formal modeling of buses in co-design systems through to software simulation and development environments. 410 0$aConcurrent systems engineering series ;$vv. 65. 606 $aParallel processing (Electronic computers)$vCongresses 606 $aoccam (Computer program language)$vCongresses 606 $aTransputers$vCongresses 606 $aComputer architecture$vCongresses 608 $aElectronic books. 615 0$aParallel processing (Electronic computers) 615 0$aoccam (Computer program language) 615 0$aTransputers 615 0$aComputer architecture 676 $a004 701 $aMcEwan$b Alistair A$0902793 712 12$aWoTUG Technical Meeting 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910451878903321 996 $aCommunicating process architectures 2007$92018135 997 $aUNINA