LEADER 01806nam 2200397 450 001 9910440254403321 005 20231208095019.0 010 $a0-7381-6283-3 024 7 $a10.1109/IEEESTD.2009.5464492 035 $a(CKB)3780000000092630 035 $a(NjHacI)993780000000092630 035 $a(EXLCZ)993780000000092630 100 $a20231208d2009 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aIEEE Std 1076.1 IEC 61691-6 Edition 1.0 2009-12 $eBehavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions /$fInstitute of Electrical and Electronics Engineers 210 1$aNew York :$cIEEE,$d2009. 215 $a1 online resource (346 pages) 330 $aThis standard defines the IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDL-AMS, is built on IEEE Std 1076¿-2002 (VHDL) and extends it with additions and changes to provide capabilities of writing and simulating analog and mixed-signal models. 517 $a61691-6-2009 - IEC/IEEE International Standard - Behavioural languages - Part 6 517 $a61691-6-2009 - Behavioural languages - Part 6 517 $aIEEE Std 61691-6 606 $aComputer hardware description languages 606 $aVHDL (Computer hardware description language) 615 0$aComputer hardware description languages. 615 0$aVHDL (Computer hardware description language) 676 $a621.38101135133 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a9910440254403321 996 $aIEEE Std 1076.1 IEC 61691-6 Edition 1.0 2009-12$92580629 997 $aUNINA