LEADER 00910nam--2200325---450 001 990000927290203316 005 20230412105203.0 010 $a88-7003-026-1 035 $a0092729 035 $aUSA010092729 035 $a(ALEPH)000092729USA01 035 $a0092729 100 $a20020130d1995----km-y0itay0103----ba 101 $aita 102 $aIT 105 $a||||||||001yy 200 1 $aNiccolò Maria Pallavicini$el'ascesa al tempio della virtù attraverso il mecenatismo$fStella Rudolph 210 $aRoma$cBozzi$d1995 215 $aXV, 253 p$cill.$d29 cm 410 $12001 606 0 $aPallavicini, Niccolò Maria 676 $a709. 700 1$aRUDOLPH,$bStella$0158023 801 0$aIT$bsalbc$gISBD 912 $a990000927290203316 951 $aXII.2.B. 814(VII P 399)$b134386 L.M.$cVII P 959 $aBK 969 $aUMA 996 $aNiccolò Maria Pallavicini$9971468 997 $aUNISA LEADER 01150nam 2200337 450 001 9910440015403321 005 20231214024958.0 010 $a1-5044-7426-0 035 $a(CKB)4100000011774093 035 $a(NjHacI)994100000011774093 035 $a(EXLCZ)994100000011774093 100 $a20231214d2009 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$a1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline /$fInstitute of Electrical and Electronics Engineers 210 1$a[Place of publication not identified] :$cIEEE,$d2009. 215 $a1 online resource 606 $aFinish hardware 606 $aHardware industry 615 0$aFinish hardware. 615 0$aHardware industry. 676 $a683 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a9910440015403321 996 $a1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline$92581488 997 $aUNINA