LEADER 03384nam 2200625Ia 450 001 9910438056903321 005 20200520144314.0 010 $a1-4614-3269-3 024 7 $a10.1007/978-1-4614-3269-2 035 $a(CKB)2560000000102934 035 $a(EBL)1694249 035 $a(OCoLC)843346163 035 $a(SSID)ssj0000904379 035 $a(PQKBManifestationID)11556697 035 $a(PQKBTitleCode)TC0000904379 035 $a(PQKBWorkID)10919894 035 $a(PQKB)11522964 035 $a(DE-He213)978-1-4614-3269-2 035 $a(MiAaPQ)EBC1694249 035 $a(iGPub)SPNA0031291 035 $a(PPN)170487369 035 $a(EXLCZ)992560000000102934 100 $a20130522d2013 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aConstraining designs for synthesis and timing analysis $ea practical guide to synopsys design constraints (SDC) /$fSridhar Gangadharan, Sanjay Churiwala 205 $a1st ed. 2013. 210 $aNew York $cSpringer$dc2013 215 $a1 online resource (245 p.) 300 $aDescription based upon print version of record. 311 $a1-4899-8916-1 311 $a1-4614-3268-5 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC. 330 $aThis book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.  ·         Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; ·         Includes key topics of interest to a synthesis, static timing analysis or  place and route engineer; ·         Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; ·         Explains fundamental concepts and provides exact command syntax. 606 $aTiming circuits 606 $aTime measurements 615 0$aTiming circuits. 615 0$aTime measurements. 676 $a004.1 676 $a620 676 $a621.381 676 $a621.3815 700 $aGangadharan$b Sridhar. $01061365 701 $aChuriwala$b Sanjay$01758945 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910438056903321 996 $aConstraining designs for synthesis and timing analysis$94197283 997 $aUNINA