LEADER 00906nam--2200325---450 001 990001711810203316 005 20230109095620.0 035 $a000171181 035 $aUSA01000171181 035 $a(ALEPH)000171181USA01 035 $a000171181 100 $a20040531d1981----km-y0itay0103----ba 101 0 $ager 102 $aDE 105 $aa|||||||001yy 200 1 $a<> deutsche Romantik$fEckart Kleßmann 210 $aKöln$cDuMont Buchverlag$d1981 215 $a229 p.$cill.$d18 cm 225 2 $aDumont Taschenbücher$v74 410 0$12001$aDumont Taschenbücher$v74 606 0 $aArte$yGermania$zSec. 19. 676 $a709.43 700 1$aKLEßMANN,$bEckart$0175628 801 0$aIT$bsalbc$gISBD 912 $a990001711810203316 951 $aXII.2.B. 141(II T B coll. 8/74)$b8501 L.M.$cII T B 959 $aBK 969 $aUMA 996 $aDeutsche Romantik$9948047 997 $aUNISA LEADER 02961nam 2200577Ia 450 001 9910438046003321 005 20170814173704.0 010 $a1-4614-0818-0 024 7 $a10.1007/978-1-4614-0818-5 035 $a(CKB)2560000000090350 035 $a(EBL)971462 035 $a(OCoLC)805724480 035 $a(SSID)ssj0000739111 035 $a(PQKBManifestationID)11458055 035 $a(PQKBTitleCode)TC0000739111 035 $a(PQKBWorkID)10687972 035 $a(PQKB)10179487 035 $a(DE-He213)978-1-4614-0818-5 035 $a(MiAaPQ)EBC971462 035 $a(PPN)168294915 035 $a(EXLCZ)992560000000090350 100 $a20120905h20122013 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aRobust SRAM designs and analysis /$fJawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan 210 $aNew York $cSpringer$d2012, c2013 215 $a1 online resource (175 p.) 300 $aDescription based upon print version of record. 311 $a1-4614-0817-2 320 $aIncludes bibliographical references and index. 327 $aIntroduction to SRAM -- Design Metrics of SRAM Bitcell -- Single-ended SRAM Bitcell Design -- 2-Port SRAM Bitcell Design -- SRAM Bitcell Design Using Unidirectional Devices -- NBTI and its Effect on SRAM. 330 $aThis book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design. 606 $aRandom access memory$xDesign 606 $aSemiconductor storage devices 615 0$aRandom access memory$xDesign. 615 0$aSemiconductor storage devices. 676 $a621.3815 676 $a621.3815/2 676 $a621.38152 700 $aSingh$b Jawar$0853118 701 $aLeal Filho$b Walter$0326246 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910438046003321 996 $aRobust SRAM designs and analysis$92501434 997 $aUNINA