LEADER 04104nam 2200529Ia 450 001 9910437959803321 005 20200520144314.0 010 $a94-91216-92-9 024 7 $a10.2991/978-94-91216-92-3 035 $a(OCoLC)880853005 035 $a(MiFhGG)GVRL6XUF 035 $a(CKB)2670000000536685 035 $a(MiAaPQ)EBC1399103 035 $a(EXLCZ)992670000000536685 100 $a20130805d2013 uy 0 101 0 $aeng 135 $aurun|---uuuua 181 $ctxt 182 $cc 183 $acr 200 10$aMulticore systems on-chip $epractical software/hardware design /$fAbderazek Ben Abdallah 205 $a2nd ed. 210 $aNew York $cSpringer$d2013 215 $a1 online resource (xxvi, 273 pages) $cillustrations (some color) 225 0$aAtlantis ambient and pervasive intelligence ;$vv. 7 300 $a"ISSN: 1875-7669." 311 $a94-91216-91-0 311 $a94-6239-050-9 320 $aIncludes bibliographical references. 327 $aIntroduction to Multicore Systems On-Chip -- Multicore SoCs Design Methods -- Multicore SoC Organization -- 2D Network-on-Chip -- 3D Network-on-Chip -- Network Interface Architecture and Design for 2D/3D NoCs -- Parallelizing Compiler for Single and Multicore Computing -- Power Optimization Techniques for Multicore SoCs -- Soft-Core Processor for Low-Power Embedded -- Dual-Execution Processor Architecture for Embedded -- Case Study: Deign of Embedded Multicore SoC. 330 $aSystem on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device?s functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processing cores and that load balancing between processing cores ? especially heterogeneous cores ? is very difficult. 410 0$aAtlantis ambient and pervasive intelligence ;$vv. 7. 606 $aSystems on a chip 606 $aSoftware architecture 615 0$aSystems on a chip. 615 0$aSoftware architecture. 676 $a004.21 676 $a006.2 676 $a006.2/2 700 $aBen Abdallah$b Abderazek$01058506 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910437959803321 996 $aMulticore systems on-chip$93871471 997 $aUNINA