LEADER 04311nam 2200661Ia 450 001 9910437897703321 005 20200520144314.0 010 $a1-283-61201-1 010 $a9786613924469 010 $a1-4614-3467-X 024 7 $a10.1007/978-1-4614-3467-2 035 $a(CKB)2670000000245726 035 $a(EBL)971451 035 $a(OCoLC)809202197 035 $a(SSID)ssj0000739030 035 $a(PQKBManifestationID)11500525 035 $a(PQKBTitleCode)TC0000739030 035 $a(PQKBWorkID)10673100 035 $a(PQKB)10151314 035 $a(DE-He213)978-1-4614-3467-2 035 $a(MiAaPQ)EBC971451 035 $a(PPN)168297434 035 $a(EXLCZ)992670000000245726 100 $a20120913h20122013 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aReference-free CMOS pipeline analog-to-digital converters /$fMichael Figueiredo, Joao Goes, Guiomar Evans 205 $a1st ed. 2013. 210 $aNew York $cSpringer$d2012, c2013 215 $a1 online resource (188 p.) 225 0 $aAnalog circuits and signal processing 300 $aDescription based upon print version of record. 311 $a1-4899-8555-7 311 $a1-4614-3466-1 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- General Overview of Pipeline Analog-to-Digital Converters -- Capacitor Mismatch-Insensitive Multiplying-DAC Topologies with Unity Feedback Factor -- Application of Circuit Enhancement Techniques to ADC Building Blocks -- Design of a 7-bit 1GS/s CMOS Two-Way Interleaved Pipeline ADC -- Integrated Prototypes and Experimental Results -- Conclusions. 330 $aThis book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits. Describes various design techniques to enhance the power and area efficiency of building blocks for multiplying digital-to-analog converter (MDAC) based ADCs, such as Pipeline, Algorithmic, and multi-step Flash; Enables analog designers to enhance the performance of a range of circuits, without employing any type of digital assistance (calibration); Includes complete design flow of an ADC based on the proposed circuits and design techniques. 410 0$aAnalog Circuits and Signal Processing,$x1872-082X 606 $aAnalog-to-digital converters 606 $aElectronic circuit design 615 0$aAnalog-to-digital converters. 615 0$aElectronic circuit design. 676 $a621.39 676 $a621.39/814 676 $a621.39814 700 $aFigueiredo Michael$01058912 701 $aGoes$b Joao$01757972 701 $aEvans$b Guiomar$01757973 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910437897703321 996 $aReference-free CMOS pipeline analog-to-digital converters$94196011 997 $aUNINA