LEADER 05751nam 22008055 450 001 9910437590403321 005 20251226202319.0 010 $a3-642-35898-5 024 7 $a10.1007/978-3-642-35898-2 035 $a(CKB)3400000000102969 035 $a(DE-He213)978-3-642-35898-2 035 $a(SSID)ssj0000878657 035 $a(PQKBManifestationID)11957870 035 $a(PQKBTitleCode)TC0000878657 035 $a(PQKBWorkID)10837166 035 $a(PQKB)10425453 035 $a(MiAaPQ)EBC3092085 035 $a(PPN)168329522 035 $a(EXLCZ)993400000000102969 100 $a20130107d2013 u| 0 101 0 $aeng 135 $aurnn#008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aComputer Engineering and Technology $e16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers /$fedited by Weixia Xu, Liquan Xiao, Pingjing Lu, Jinwen Li, Chengyi Zhang 205 $a1st ed. 2013. 210 1$aBerlin, Heidelberg :$cSpringer Berlin Heidelberg :$cImprint: Springer,$d2013. 215 $a1 online resource (XIV, 263 p. 164 illus.) 225 1 $aCommunications in Computer and Information Science,$x1865-0937 ;$v337 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a3-642-35897-7 320 $aIncludes bibliographical references and index. 327 $aSession 1: Microprocessor and Implementation -- A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU -- Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method -- MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processer -- An Efficient Parallel SURF Algorithm for Multi-core Processor -- A Study of Cache Design in Stream Processor -- Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor -- Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecture -- ADL and High Performance Processor Design -- Session 2: Design of Integration Circuit -- The Design of the ROHC Header Compression Accelerator -- A Hardware Implementation of Nussinov RNA Folding Algorithm -- A Configurable Architecture for 1-D Discrete Wavelet Transform -- A Comparison of Folded Architectures for the Discrete Wavelet Transform -- A High Performance DSP System with Fault Tolerant for Space Missions -- The Design and Realization of Campus Information Release Platform Based on Android Framework -- A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method -- Session 3: I/O Interconnect -- DAMQ Sharing Scheme for Two Physical Channels in High Performance Router -- Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip -- HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip -- Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator -- A Quick Method for Mapping Cores Onto 2D-Mesh Based Networks on Chip -- Session 4: Measurement, Verification, and Others -- A Combined Hardware/Software Measurement for ARM Program Execution Time -- A Low-Complexity Parallel Two-Sided Jacobi Complex SVD Algorithm and Architecture for MIMO Beamforming Systems -- A Thermal-Aware Task Mapping Algorithm for Coarse Grain Reconfigurable Computing System -- DC Offset Mismatch Calibration for Time-Interleaved ADCs in High-Speed OFDM Receivers -- An Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures -- Memristor Working Condition Analysis Based on SPICE Model -- On Stepsize of Fast Subspace Tracking Methods. 330 $aThis book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others. 410 0$aCommunications in Computer and Information Science,$x1865-0937 ;$v337 606 $aMicroprocessors 606 $aComputer architecture 606 $aComputer arithmetic and logic units 606 $aComputer storage devices 606 $aMemory management (Computer science) 606 $aLogic design 606 $aComputers 606 $aProcessor Architectures 606 $aArithmetic and Logic Structures 606 $aComputer Memory Structure 606 $aLogic Design 606 $aHardware Performance and Reliability 615 0$aMicroprocessors. 615 0$aComputer architecture. 615 0$aComputer arithmetic and logic units. 615 0$aComputer storage devices. 615 0$aMemory management (Computer science). 615 0$aLogic design. 615 0$aComputers. 615 14$aProcessor Architectures. 615 24$aArithmetic and Logic Structures. 615 24$aComputer Memory Structure. 615 24$aLogic Design. 615 24$aHardware Performance and Reliability. 676 $a004.1 702 $aXu$b Weixia$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aXiao$b Liquan$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aLu$b Pingjing$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aLi$b Jinwen$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aZhang$b Chengyi$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a9910437590403321 996 $aComputer Engineering and Technology$91939209 997 $aUNINA