LEADER 00855nam0 2200265 450 001 9910436859203321 005 20210406134415.0 100 $a20210217d2016----km y0itay50 ba 101 0 $aita 102 $aIT 105 $a 001yy 200 1 $aProcédure civile luxembourgeoise$eapproche comparative$fSéverine Menétrey$gpréface de Thierry Hoscheit 210 $aBruxelles$cLarcier$d2016 215 $a533 p.$d24 cm 225 1 $aCollection de la Faculté de droit, d'économie et de finance de l'Université du Luxembourg 676 $a347.493 505$v22 700 1$aMenétrey,$bSéverine$0790698 702 1$aHoscheit,$bThierry 801 0$aIT$bUNINA$gREICAT$2UNIMARC 901 $aBK 912 $a9910436859203321 952 $aXX-41$b235-21$fDDRC 959 $aDDRC 996 $aProcédure civile luxembourgeoise$91766163 997 $aUNINA LEADER 04755nam 22007454a 450 001 9911019217303321 005 20250324164435.0 010 $a9786610448104 010 $a9781280448102 010 $a1280448105 010 $a9780470324899 010 $a0470324899 010 $a9780471786412 010 $a0471786411 010 $a9780471786399 010 $a047178639X 024 7 $a10.1002/0471786411 035 $a(CKB)1000000000355158 035 $a(EBL)257217 035 $a(SSID)ssj0000239863 035 $a(PQKBManifestationID)11236432 035 $a(PQKBTitleCode)TC0000239863 035 $a(PQKBWorkID)10251669 035 $a(PQKB)11362835 035 $a(MiAaPQ)EBC257217 035 $a(CaBNVSL)mat05237648 035 $a(IDAMS)0b00006481095a71 035 $a(IEEE)5237648 035 $a(OCoLC-P)1398335597 035 $a(PPN)150693044 035 $a(CaSebORM)9780471720928 035 $a(OCoLC)85820978 035 $a(OCoLC)69253176 035 $a(OCoLC-P)69253176 035 $a(Perlego)2774269 035 $a(EXLCZ)991000000000355158 100 $a20050901d2006 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aRTL hardware design using VHDL $ecoding for efficiency, portability, and scalability /$fPong P. Chu 205 $a[First edition]. 210 $aHoboken, N.J. $cWiley-Interscience$dc2006 215 $a1 online resource (695 p.) 300 $aDescription based upon print version of record. 311 08$a9780471720928 311 08$a0471720925 320 $aIncludes bibliographical references (p. 665-666) and index. 327 $aIntroduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice. 330 $aThe skills and guidance needed to master RTL hardware design This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module-level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the module-level design and can be synthesized into efficient gate-level implementation. Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices. With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper-level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today's synthesis software and FPGA devices should also refer to this book. 606 $aDigital electronics$xData processing 606 $aVHDL (Computer hardware description language) 615 0$aDigital electronics$xData processing. 615 0$aVHDL (Computer hardware description language) 676 $a621.39/2 700 $aChu$b Pong P.$f1959-$0521922 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9911019217303321 996 $aRTL hardware design using VHDL$94063180 997 $aUNINA