LEADER 03578nam 22005895 450 001 9910407735903321 005 20200630074403.0 010 $a981-15-4405-0 024 7 $a10.1007/978-981-15-4405-7 035 $a(CKB)5280000000218705 035 $a(MiAaPQ)EBC6225699 035 $a(DE-He213)978-981-15-4405-7 035 $a(PPN)248594044 035 $a(EXLCZ)995280000000218705 100 $a20200610d2020 u| 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aSystemVerilog for Hardware Description $eRTL Design and Verification /$fby Vaibbhav Taraate 205 $a1st ed. 2020. 210 1$aSingapore :$cSpringer Singapore :$cImprint: Springer,$d2020. 215 $a1 online resource (258 pages) 311 $a981-15-4404-2 327 $aChapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA. 330 $aThis book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC. 606 $aElectronic circuits 606 $aMicroprogramming 606 $aElectronics 606 $aMicroelectronics 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aControl Structures and Microprogramming$3https://scigraph.springernature.com/ontologies/product-market-codes/I12018 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aElectronic Circuits and Devices$3https://scigraph.springernature.com/ontologies/product-market-codes/P31010 615 0$aElectronic circuits. 615 0$aMicroprogramming. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aCircuits and Systems. 615 24$aControl Structures and Microprogramming. 615 24$aElectronics and Microelectronics, Instrumentation. 615 24$aElectronic Circuits and Devices. 676 $a621.392 700 $aTaraate$b Vaibbhav$4aut$4http://id.loc.gov/vocabulary/relators/aut$0788080 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910407735903321 996 $aSystemVerilog for Hardware Description$91999204 997 $aUNINA