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024 7 $a10.1007/978-3-030-44282-8
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035   $a(DE-He213)978-3-030-44282-8
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035   $a(PPN)248397788
035   $a(EXLCZ)994100000011219617
100   $a20200504d2020      u|         0
101 0 $aeng
135   $aurnn|008mamaa
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aAutomated Analysis of Virtual Prototypes at the Electronic System Level $eDesign Understanding and Applications /$fby Mehran Goli, Rolf Drechsler
205   $a1st ed. 2020.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2020.
215   $a1 online resource (XXI, 166 p. 53 illus.) 
311   $a3-030-44281-0 
327   $aChapter 1. Introduction -- Chapter 2. Background -- Chapter 3. Design Understanding Methodology -- Chapter 4. Application I: Verification -- Chapter 5. Application II: Security Validation -- Chapter 6. Application III: Design Space Exploration -- Chapter 7. Conclusion.
330   $aThis book describes a set of SystemC?based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process. Provides an extensive introduction to the field of SystemC?based virtual prototype (VP) analysis at the electronic system level; Describes a design understanding methodology from both debugger-based and compiler?based perspectives; Illustrates a semi?formal verification approach to check the validity of a given VP against its specification, user?defined rules and protocol; Discusses a security validation approach to validate the run?time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity); Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels.
606   $aElectronic circuits
606   $aComputer engineering
606   $aInternet of things
606   $aEmbedded computer systems
606   $aMicroprocessors
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aCyber-physical systems, IoT$3https://scigraph.springernature.com/ontologies/product-market-codes/T24080
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
615  0$aElectronic circuits.
615  0$aComputer engineering.
615  0$aInternet of things.
615  0$aEmbedded computer systems.
615  0$aMicroprocessors.
615 14$aCircuits and Systems.
615 24$aCyber-physical systems, IoT.
615 24$aProcessor Architectures.
676   $a005.1028
676   $a620.0042
700   $aGoli$b Mehran$4aut$4http://id.loc.gov/vocabulary/relators/aut$0908692
702   $aDrechsler$b Rolf$4aut$4http://id.loc.gov/vocabulary/relators/aut
801  0$bMiAaPQ
801  1$bMiAaPQ
801  2$bMiAaPQ
906   $aBOOK
912   $a9910403768303321
996   $aAutomated Analysis of Virtual Prototypes at the Electronic System Level$92032248
997   $aUNINA