LEADER 03425nam  22005535  450 
001 9910366590403321
005 20200701150354.0
010   $a3-030-18026-3
024 7 $a10.1007/978-3-030-18026-3
035   $a(CKB)4100000008280526
035   $a(MiAaPQ)EBC5779974
035   $a(DE-He213)978-3-030-18026-3
035   $a(PPN)236525786
035   $a(EXLCZ)994100000008280526
100   $a20190522d2020      u|             0
101 0 $aeng
135   $aurcnu||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aIn-Memory Computing$b[electronic resource] $eSynthesis and Optimization /$fby Saeideh Shirinzadeh, Rolf Drechsler
205   $a1st ed. 2020.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2020.
215   $a1 online resource (121 pages) $cillustrations
311   $a3-030-18025-5 
320   $aIncludes bibliographical references and index.
327   $aChapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions.
330   $aThis book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
606   $aElectronic circuits
606   $aMicroprocessors
606   $aElectronics
606   $aMicroelectronics
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
606   $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027
615  0$aElectronic circuits.
615  0$aMicroprocessors.
615  0$aElectronics.
615  0$aMicroelectronics.
615 14$aCircuits and Systems.
615 24$aProcessor Architectures.
615 24$aElectronics and Microelectronics, Instrumentation.
676   $a004.5
700   $aShirinzadeh$b Saeideh$4aut$4http://id.loc.gov/vocabulary/relators/aut$0973110
702   $aDrechsler$b Rolf$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910366590403321
996   $aIn-Memory Computing$92213996
997   $aUNINA