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010   $a3-030-31310-7
024 7 $a10.1007/978-3-030-31310-4
035   $a(CKB)5280000000190185
035   $a(MiAaPQ)EBC6000724
035   $a(DE-He213)978-3-030-31310-4
035   $a(PPN)242820352
035   $a(EXLCZ)995280000000190185
100   $a20191220d2020      u|         0
101 0 $aeng
135   $aurcnu||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aDesign and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures /$fby Kanchan Manna, Jimson Mathew
205   $a1st ed. 2020.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2020.
215   $a1 online resource
311   $a3-030-31309-3 
320   $aIncludes bibliographical references and index.
327   $aIntroduction to Network-on-Chip Designs and Tests -- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems -- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems -- Temperature-aware design strategy for 3D-NoC-based multicore systems -- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems.
330   $aThis book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.
606   $aElectronic circuits
606   $aMicroprocessors
606   $aElectronics
606   $aMicroelectronics
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
606   $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027
615  0$aElectronic circuits.
615  0$aMicroprocessors.
615  0$aElectronics.
615  0$aMicroelectronics.
615 14$aCircuits and Systems.
615 24$aProcessor Architectures.
615 24$aElectronics and Microelectronics, Instrumentation.
676   $a621.381531
676   $a621.381531
700   $aManna$b Kanchan$4aut$4http://id.loc.gov/vocabulary/relators/aut$01062637
702   $aMathew$b Jimson$4aut$4http://id.loc.gov/vocabulary/relators/aut
801  0$bMiAaPQ
801  1$bMiAaPQ
801  2$bMiAaPQ
906   $aBOOK
912   $a9910366580003321
996   $aDesign and Test Strategies for 2D$92527186
997   $aUNINA