LEADER 02778nam  2200421   450 
001 9910350232503321
005 20190220151420.0
010   $a981-13-6362-5
024 7 $a10.1007/978-981-13-6362-7
035   $a(CKB)4100000007656669
035   $a(DE-He213)978-981-13-6362-7
035   $a(MiAaPQ)EBC5716832
035   $a(EXLCZ)994100000007656669
100   $a20190309d2019      uy             0
101 0 $aeng
135   $aurnn|008mamaa
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aMassive MIMO detection algorithm and VLSI architecture /$fLeibo Liu, Guiqiang Peng, Shaojun Wei
210  1$aBeijing ;$aSingapore :$cScience Press :$cSpringer,$d2019.
215   $a1 online resource (XVI, 336 p. 186 illus., 120 illus. in color.) 
311   $a981-13-6361-7 
327   $aChapter 1 Introduction -- Chapter 2 Linear Massive MIMO Detection Algorithm -- Chapter 3 Architecture of Linear Massive MIMO Detection -- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm -- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection -- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection -- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.
330   $aThis book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method. .
606   $aMIMO systems
615  0$aMIMO systems.
676   $a004
700   $aLiu$b Leibo$01060030
702   $aPeng$b Guiqiang
702   $aWei$b Shaojun
801  0$bMiAaPQ
801  1$bMiAaPQ
801  2$bMiAaPQ
906   $aBOOK
912   $a9910350232503321
996   $aMassive MIMO detection algorithm and VLSI architecture$92510240
997   $aUNINA