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200 10$aBehavioural languages$hPart 4$iVerilog hardware description language /$fInstitute of Electrical and Electronics Engineers
210  1$aNew York, New York :$cIEEE,$d2004.
215   $a1 online resource
225 1 $aIEEE Std ;$v1364
330   $aThe Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
410  0$aIEEE Std ;$v1364.
517   $a61691-4-2004 - IEC 61691-4 Ed.1 
606   $aVerilog (Computer hardware description language)
606   $aVHDL (Computer hardware description language)
615  0$aVerilog (Computer hardware description language)
615  0$aVHDL (Computer hardware description language)
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