LEADER 01624nam 2200349 450 001 9910349358103321 005 20231209100040.0 010 $a0-7381-4779-6 024 7 $a10.1109/IEEESTD.2005.8894298 035 $a(CKB)4100000009825464 035 $a(NjHacI)994100000009825464 035 $a(EXLCZ)994100000009825464 100 $a20231209d2005 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$a62050-2005 - IEC/IEEE international standard - VHDL Register Transfer Level (RTL) synthesis /$fInstitute of Electrical and Electronics Engineers 210 1$aNew York, New York :$cIEEE,$d2005. 215 $a1 online resource (128 pages) 330 $aReplaces IEEE Std 1076.6-2004. This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors. 517 $a62050-2005 - IEC/IEEE International Standard - VHDL Register Transfer Level 606 $aVHDL (Computer hardware description language) 615 0$aVHDL (Computer hardware description language) 676 $a621.392 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a9910349358103321 996 $a62050-2005 - IEC$92584857 997 $aUNINA