LEADER 04080nam 22005415 450 001 9910337649803321 005 20200703050546.0 010 $a3-319-98116-1 024 7 $a10.1007/978-3-319-98116-1 035 $a(CKB)4100000006098284 035 $a(MiAaPQ)EBC5507952 035 $a(DE-He213)978-3-319-98116-1 035 $a(PPN)230542395 035 $a(EXLCZ)994100000006098284 100 $a20180901d2019 u| 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aPost-Silicon Validation and Debug /$fedited by Prabhat Mishra, Farimah Farahmandi 205 $a1st ed. 2019. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2019. 215 $a1 online resource (393 pages) 311 $a3-319-98115-3 327 $aPart 1. Introduction -- Post-Silicon SoC Validation Challenges -- Part 2. Debug Infrastructure -- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness -- Structure-based Signal Selection for Post-silicon Validation -- Simulation-based Signal Selection -- Hybrid Signal Selection -- Post-Silicon Signal Selection using Machine Learning -- Part 3. Generation of Tests and Assertions -- Observability-aware Post-Silicon Test Generation -- On-chip Constrained-Random Stimuli Generation -- Test Generation and Lightweight Checking for Multi-core Memory Consistency -- Selection of Post-Silicon Hardware Assertions -- Part 4. Post-Silicon Debug -- Debug Data Reduction Techniques -- High-level Debugging of Post-silicon Failures -- Post-silicon Fault Localization with Satisfiability Solvers -- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes -- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis -- Part 5. Case Studies -- Network-on-Chip Validation and Debug -- Post-silicon Validation of the IBM Power8 Processor -- Part 6. Conclusion and Future Directions -- SoC Security versus Post-Silicon Debug Conflict -- The Future of Post-Silicon Debug. 330 $aThis book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. Provides a comprehensive overview of the SoC post-silicon validation and debug challenges; Covers state-of-the-art techniques for developing on-chip debug infrastructure; Describes automated techniques for generating post-silicon tests and assertions to enable effective post-silicon debug and coverage analysis; Covers scalable post-silicon validation and bug localization using a combination of simulation-based techniques and formal methods; Presents case studies for post-silicon debug of industrial SoC designs. 606 $aElectronic circuits 606 $aMicroprocessors 606 $aElectronics 606 $aMicroelectronics 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a005.14 702 $aMishra$b Prabhat$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aFarahmandi$b Farimah$4edt$4http://id.loc.gov/vocabulary/relators/edt 906 $aBOOK 912 $a9910337649803321 996 $aPost-Silicon Validation and Debug$92177702 997 $aUNINA