LEADER 03814nam 22005055 450 001 9910337625503321 005 20200704174852.0 010 $a3-030-20721-8 024 7 $a10.1007/978-3-030-20721-2 035 $a(CKB)4100000008340218 035 $a(MiAaPQ)EBC5782508 035 $a(DE-He213)978-3-030-20721-2 035 $a(PPN)236520091 035 $a(EXLCZ)994100000008340218 100 $a20190530d2019 u| 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aFPGA-BASED Hardware Accelerators /$fby Iouliia Skliarova, Valery Sklyarov 205 $a1st ed. 2019. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2019. 215 $a1 online resource (257 pages) $cillustrations 225 1 $aLecture Notes in Electrical Engineering,$x1876-1100 ;$v566 311 $a3-030-20720-X 327 $aReconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design. 330 $aThis book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design. 410 0$aLecture Notes in Electrical Engineering,$x1876-1100 ;$v566 606 $aElectronic circuits 606 $aComputational intelligence 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aComputational Intelligence$3https://scigraph.springernature.com/ontologies/product-market-codes/T11014 615 0$aElectronic circuits. 615 0$aComputational intelligence. 615 14$aCircuits and Systems. 615 24$aComputational Intelligence. 676 $a621.395 676 $a621.395 700 $aSkliarova$b Iouliia$4aut$4http://id.loc.gov/vocabulary/relators/aut$0867181 702 $aSklyarov$b Valery$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910337625503321 996 $aFPGA-BASED Hardware Accelerators$91935507 997 $aUNINA