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001 9910299944003321
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010   $a3-319-73909-3
024 7 $a10.1007/978-3-319-73909-0
035   $a(CKB)4100000002485446
035   $a(MiAaPQ)EBC5309353
035   $a(DE-He213)978-3-319-73909-0
035   $a(PPN)224640879
035   $a(EXLCZ)994100000002485446
100   $a20180222d2018      u|         0
101 0 $aeng
135   $aurcnu||||||||
181   $2rdacontent
182   $2rdamedia
183   $2rdacarrier
200 10$aSymbolic Parallelization of Nested Loop Programs /$fby Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich
205   $a1st ed. 2018.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2018.
215   $a1 online resource (184 pages) $cillustrations (some color)
311   $a3-319-73908-5 
320   $aIncludes bibliographical references and index.
327   $aIntroduction -- Fundamentals and Compiler Framework -- Symbolic Parallelization -- Symbolic Multi?level Parallelization -- On?demand Fault?tolerant Loop Processing -- Conclusions.
330   $aThis book introduces new compilation techniques, using the polyhedron model for the resource-adaptive parallel execution of loop programs on massively parallel processor arrays. The authors show how to compute optimal symbolic assignments and parallel schedules of loop iterations at compile time, for cases where the number of available cores becomes known only at runtime. The compile/runtime symbolic parallelization approach the authors describe reduces significantly the runtime overhead, compared to dynamic or just?in-time compilation. The new, on?demand fault?tolerant loop processing approach described in this book protects loop nests for parallel execution against soft errors. .
606   $aElectronic circuits
606   $aMicroprocessors
606   $aElectronics
606   $aMicroelectronics
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
606   $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027
615  0$aElectronic circuits.
615  0$aMicroprocessors.
615  0$aElectronics.
615  0$aMicroelectronics.
615 14$aCircuits and Systems.
615 24$aProcessor Architectures.
615 24$aElectronics and Microelectronics, Instrumentation.
676   $a005.275
700   $aTanase$b Alexandru-Petru$4aut$4http://id.loc.gov/vocabulary/relators/aut$01063084
702   $aHannig$b Frank$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aTeich$b Jürgen$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910299944003321
996   $aSymbolic Parallelization of Nested Loop Programs$92530032
997   $aUNINA