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010   $a3-319-59418-4
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035   $a(DE-He213)978-3-319-59418-7
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035   $a(PPN)202994031
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100   $a20170628d2018      u|         0
101 0 $aeng
135   $aurnn|008mamaa
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aASIC/SoC Functional Design Verification $eA Comprehensive Guide to Technologies and Methodologies /$fby Ashok B. Mehta
205   $a1st ed. 2018.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2018.
215   $a1 online resource (XXXI, 328 p. 175 illus., 160 illus. in color.) 
311   $a3-319-59417-6 
327   $aChapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based.
330   $aThis book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
606   $aElectronic circuits
606   $aMicroprocessors
606   $aLogic design
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
606   $aLogic Design$3https://scigraph.springernature.com/ontologies/product-market-codes/I12050
615  0$aElectronic circuits.
615  0$aMicroprocessors.
615  0$aLogic design.
615 14$aCircuits and Systems.
615 24$aProcessor Architectures.
615 24$aLogic Design.
676   $a621.3815
700   $aMehta$b Ashok B$4aut$4http://id.loc.gov/vocabulary/relators/aut$0763798
906   $aBOOK
912   $a9910299911803321
996   $aASIC$92501139
997   $aUNINA