LEADER 03917nam  22006255  450 
001 9910299853303321
005 20200705003233.0
010   $a3-319-09309-6
024 7 $a10.1007/978-3-319-09309-3
035   $a(CKB)3710000000249016
035   $a(EBL)1965453
035   $a(OCoLC)892484660
035   $a(SSID)ssj0001353949
035   $a(PQKBManifestationID)11773467
035   $a(PQKBTitleCode)TC0001353949
035   $a(PQKBWorkID)11317543
035   $a(PQKB)11094452
035   $a(DE-He213)978-3-319-09309-3
035   $a(MiAaPQ)EBC1965453
035   $a(PPN)181348276
035   $a(EXLCZ)993710000000249016
100   $a20140925d2015      u|         0
101 0 $aeng
135   $aur|n|---|||||
181   $ctxt
182   $cc
183   $acr
200 10$aDebug Automation from Pre-Silicon to Post-Silicon /$fby Mehdi Dehbashi, Görschwin Fey
205   $a1st ed. 2015.
210  1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2015.
215   $a1 online resource (180 p.)
300   $aDescription based upon print version of record.
311   $a3-319-09308-8 
320   $aIncludes bibliographical references and index.
327   $aIntroduction -- Preliminaries -- Part I Debug of Design Bugs -- Automated Debugging for Logic Bugs -- Automated Debugging from Pre-Silicon to Post-Silicon -- Automated Debugging for Synchronization Bugs -- Part II Debug of Delay Faults -- Analyzing Timing Variations -- Automated Debugging for Timing Variations -- Efficient Automated Speedpath Debugging -- Part III Debug of Transactions -- Online Debug for NoC-Based Multiprocessor SoCs -- Summary and Outlook.
330   $aThis book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential fault candidates at RTL and gate-level of a circuit. Debug techniques for logic bugs and synchronization bugs are demonstrated, enabling readers to localize the most difficult bugs. Debug automation for electrical faults (delay faults)finds the potentially failing speedpaths in a circuit at gate-level. The various debug approaches described achieve high diagnosis accuracy and reduce the debugging time, shortening the IC development cycle and increasing the productivity of designers. Describes a unified framework for debug automation used at both pre-silicon and post-silicon stages; Provides approaches for debug automation of a hardware system at different levels of abstraction, i.e., chip, gate-level, RTL and transaction level; Includes techniques for debug automation of design bugs and electrical faults, as well as an infrastructure to debug NoC-based multiprocessor SoCs.
606   $aElectronic circuits
606   $aMicroprocessors
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
606   $aElectronic Circuits and Devices$3https://scigraph.springernature.com/ontologies/product-market-codes/P31010
615  0$aElectronic circuits.
615  0$aMicroprocessors.
615 14$aCircuits and Systems.
615 24$aProcessor Architectures.
615 24$aElectronic Circuits and Devices.
676   $a004.1
676   $a620
676   $a621.3815
700   $aDehbashi$b Mehdi$4aut$4http://id.loc.gov/vocabulary/relators/aut$01062542
702   $aFey$b Görschwin$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910299853303321
996   $aDebug Automation from Pre-Silicon to Post-Silicon$92526422
997   $aUNINA