LEADER 04934nam 22006375 450 001 9910299847903321 005 20200706220928.0 010 $a3-319-07139-4 024 7 $a10.1007/978-3-319-07139-8 035 $a(CKB)3710000000225350 035 $a(EBL)1802619 035 $a(SSID)ssj0001338599 035 $a(PQKBManifestationID)11776626 035 $a(PQKBTitleCode)TC0001338599 035 $a(PQKBWorkID)11338221 035 $a(PQKB)10481266 035 $a(DE-He213)978-3-319-07139-8 035 $a(MiAaPQ)EBC1802619 035 $a(PPN)180622153 035 $a(EXLCZ)993710000000225350 100 $a20140823d2015 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aSVA: The Power of Assertions in SystemVerilog /$fby Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny 205 $a2nd ed. 2015. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2015. 215 $a1 online resource (589 p.) 300 $aDescription based upon print version of record. 311 $a1-322-13632-7 311 $a3-319-07138-6 320 $aIncludes bibliographical references and index. 327 $aPart I. Opening -- Introduction -- System Verilog Language and Overview -- System Verilog Simulation Semantics -- Part II. Basic Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Part III. Metalanguage Constructs -- Let, Sequence and Property Declarations; Inference.- Checkers -- Part IV. Advanced Assertions -- Advanced Properties -- Advanced Sequences.- Clocks -- Resets -- Procedural Concurrent Assertions.- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Part V. Formal Verification -- Introduction to Assertion-Based Formal Verification.- Formal Verification and Models.- Formal Semantics.- Part VI. Advanced Checkers -- Checkers in Formal Verification.- Checker Libraries -- Appendix -- References.- Index. 330 $aThis book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA).  It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis.  The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties.  The book also shows how SVA fits into the broader SystemVerilog language, demonstrating the ways that assertions can interact with other SystemVerilog components.  The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play.  This second edition covers the features introduced by the recent IEEE 1800-2012 SystemVerilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists, and EDA tool developers.  With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.  ·         Provides a comprehensive guide to assertion-based verification with SystemVerilog Assertions (SVA); ·         Includes step-by-step examples of how SVA can be used to construct powerful  and reusable sets of properties; ·         Covers the entire SVA language with all the recent enhancements of the IEEE 1800-2012 SystemVerilog standard. 606 $aElectronic circuits 606 $aMicroprocessors 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aElectronic Circuits and Devices$3https://scigraph.springernature.com/ontologies/product-market-codes/P31010 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronic Circuits and Devices. 676 $a004.1 676 $a621.381548 700 $aCerny$b Eduard$4aut$4http://id.loc.gov/vocabulary/relators/aut$01064703 702 $aDudani$b Surrendra$4aut$4http://id.loc.gov/vocabulary/relators/aut 702 $aHavlicek$b John$4aut$4http://id.loc.gov/vocabulary/relators/aut 702 $aKorchemny$b Dmitry$4aut$4http://id.loc.gov/vocabulary/relators/aut 906 $aBOOK 912 $a9910299847903321 996 $aSVA: The Power of Assertions in SystemVerilog$92540263 997 $aUNINA