LEADER 03822nam 22006615 450 001 9910299830503321 005 20200630022841.0 010 $a1-4614-1323-0 024 7 $a10.1007/978-1-4614-1323-3 035 $a(CKB)3710000000433391 035 $a(EBL)2093156 035 $a(SSID)ssj0001524979 035 $a(PQKBManifestationID)11859581 035 $a(PQKBTitleCode)TC0001524979 035 $a(PQKBWorkID)11485357 035 $a(PQKB)11184446 035 $a(DE-He213)978-1-4614-1323-3 035 $a(MiAaPQ)EBC2093156 035 $a(PPN)186394012 035 $a(EXLCZ)993710000000433391 100 $a20150612d2015 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aLow Power Interconnect Design /$fby Sandeep Saini 205 $a1st ed. 2015. 210 1$aNew York, NY :$cSpringer New York :$cImprint: Springer,$d2015. 215 $a1 online resource (166 p.) 300 $aDescription based upon print version of record. 311 $a1-4614-1322-2 320 $aIncludes bibliographical references. 327 $aPart I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques. 330 $aThis book provides practical solutions for delay and power reduction for on-chip interconnects and buses.  It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.  Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.   ·         Provides practical solutions for delay and power reduction for on-chip interconnects and buses; ·         Focuses on Deep Sub micron technology devices and interconnects; ·         Offers in depth analysis of delay, including details regarding crosstalk and parasitics;  ·         Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; ·         Provides detailed simulation results to support the theoretical discussions. ·         Provides details of delay and power efficient bus coding techniques. 606 $aElectronic circuits 606 $aElectronics 606 $aMicroelectronics 606 $aMicroprocessors 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 615 0$aElectronic circuits. 615 0$aElectronics. 615 0$aMicroelectronics. 615 0$aMicroprocessors. 615 14$aCircuits and Systems. 615 24$aElectronics and Microelectronics, Instrumentation. 615 24$aProcessor Architectures. 676 $a004.1 676 $a620 676 $a621.381 676 $a621.3815 700 $aSaini$b Sandeep$4aut$4http://id.loc.gov/vocabulary/relators/aut$0739877 906 $aBOOK 912 $a9910299830503321 996 $aLow Power Interconnect Design$91466036 997 $aUNINA