LEADER 00990nam0-22003371i-450- 001 990006864790403321 005 20001010 010 $a88-420-5467-4 035 $a000686479 035 $aFED01000686479 035 $a(Aleph)000686479FED01 035 $a000686479 100 $a20001010d--------km-y0itay50------ba 101 0 $aita 105 $ay-------001yy 200 1 $aCome nella boxe$elo spettacolo della politica in Tv$fOmar Calabrese. 210 $aRoma-Bari$cLaterza$d1998. 215 $a140 p. 18 cm 225 1 $aSaggi tascabili Laterza$v219 610 0 $aPropaganda politica - Mezzi di informazione - Italia 610 0 $aPolitica - Trasmissioni televisive - Italia 676 $a324.730945 700 1$aCalabrese,$bOmar$f<1949-2012>$038779 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990006864790403321 952 $aCOLLEZ. 94 (219)$b32419$fFSPBC 959 $aFSPBC 996 $aCome nella boxe$9624921 997 $aUNINA DB $aGEN01 LEADER 03959nam 22006615 450 001 9910299815403321 005 20200703121742.0 010 $a9783319179247 024 7 $a10.1007/978-3-319-17924-7 035 $a(CKB)2670000000618814 035 $a(EBL)2094785 035 $a(SSID)ssj0001501201 035 $a(PQKBManifestationID)11808247 035 $a(PQKBTitleCode)TC0001501201 035 $a(PQKBWorkID)11522719 035 $a(PQKB)10540242 035 $a(DE-He213)978-3-319-17924-7 035 $a(MiAaPQ)EBC2094785 035 $a(PPN)186026706 035 $a(EXLCZ)992670000000618814 100 $a20150519d2015 u| 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aFPGA Design $eBest Practices for Team-based Reuse /$fby Philip Andrew Simpson 205 $a2nd ed. 2015. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2015. 215 $a1 online resource (260 p.) 300 $aDescription based upon print version of record. 311 $a3-319-17924-1 311 $a3-319-17923-3 327 $aIntroduction -- Project Management -- Design Specification -- System Modeling -- Resource Scoping -- Design Environment -- Board Design -- Power and Thermal analysis -- Team Based Design -- RTL Design -- IP reuse -- Embedded Design -- Functional verification -- Timing Closure -- High level  Design -- In System Debug -- Design Sign-off. 330 $aThis book describes best practices for successful FPGA design. It is the result of the author?s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book?s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expanded to include more up to date techniques as well as providing more extensive scripts and RTL code that can be reused by readers. Presents complete, field-tested methodology for FPGA design, focused on reuse across design teams; Offers best practices for FPGA timing closure, in-system debug, and board design; Details techniques to resolve common pitfalls in designing with FPGAs. 606 $aElectronic circuits 606 $aMicroprocessors 606 $aElectronics 606 $aMicroelectronics 606 $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068 606 $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014 606 $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027 615 0$aElectronic circuits. 615 0$aMicroprocessors. 615 0$aElectronics. 615 0$aMicroelectronics. 615 14$aCircuits and Systems. 615 24$aProcessor Architectures. 615 24$aElectronics and Microelectronics, Instrumentation. 676 $a004.1 676 $a620 676 $a621.381 676 $a621.3815 700 $aSimpson$b Philip Andrew$4aut$4http://id.loc.gov/vocabulary/relators/aut$0720575 906 $aBOOK 912 $a9910299815403321 996 $aFPGA Design$91412227 997 $aUNINA