LEADER 03549oam 2200517 450 001 9910299745103321 005 20190911103512.0 010 $a1-4614-4963-4 024 7 $a10.1007/978-1-4614-4963-8 035 $a(OCoLC)861534722 035 $a(MiFhGG)GVRL6XUM 035 $a(EXLCZ)992670000000427488 100 $a20130719d2014 uy 0 101 0 $aeng 135 $aurun|---uuuua 181 $ctxt 182 $cc 183 $acr 200 10$aHigh performance multi-channel high-speed I/O circuits /$fTaehyoun Oh, Ramesh Harjani 205 $a1st ed. 2014. 210 1$aNew York :$cSpringer,$d2014. 215 $a1 online resource (x, 89 pages) $cillustrations (some color) 225 1 $aAnalog Circuits and Signal Processing,$x1872-082X 300 $a"ISSN: 1872-082X." 311 $a1-4614-4962-6 320 $aIncludes bibliographical references. 327 $aIntroduction -- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process -- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process -- Adaptive XTCR, AGC, and Adaptive DFE Loop -- Research Summary & Contributions -- References -- Appendix A: Noise Analysis -- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (? 4) -- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter -- Appendix D: Line Mismatch Sensitivity -- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench -- Appendix F: Bandwidth Improvement by Technology Scaling. 330 $aThis book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds.  This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. ·         Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits; ·         Includes critical background knowledge related to channel ISI equalization circuits; ·         Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems. 410 0$aAnalog Circuits and Signal Processing,$x1872-082X 606 $aSignal processing 606 $aElectronic circuit design 606 $aElectromagnetic interference$xPrevention 606 $aCrosstalk$xPrevention 615 0$aSignal processing. 615 0$aElectronic circuit design. 615 0$aElectromagnetic interference$xPrevention. 615 0$aCrosstalk$xPrevention. 676 $a621.3822 700 $aOh$b Taehyoun$4aut$4http://id.loc.gov/vocabulary/relators/aut$0875354 702 $aHarjani$b Ramesh$f1959- 801 0$bMiFhGG 801 1$bMiFhGG 906 $aBOOK 912 $a9910299745103321 996 $aHigh Performance Multi-Channel High-Speed I$91954342 997 $aUNINA